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US 11,637,209 B2Granted
JFET with implant isolation
AssigneeNexgen Power Systems, Inc.
InventorsClifford Drowley, Andrew P. Edwards, Subhash Srinivas Pidaparthi, Ray Milano
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Abstract
A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.
Claims16
A vertical junction field effect transistor (JFET), comprising:
- a substrate;
- an active region comprising a plurality of semiconductor fins;
- a source metal layer electrically coupled to a surface of the semiconductor fins;
- a source metal pad layer coupled to the semiconductor fins through the source metal layer;
- a gate region surrounding the semiconductor fins;
- and
- a body diode surrounding the gate region.
4 more elements
A semiconductor device, comprising:
- a substrate comprising an n+ GaN layer;
- a drift layer coupled to the substrate and comprising an n− GaN layer;
- a plurality of fins comprising an n GaN material and coupled to the drift layer;
- a gate layer comprising a p GaN material and surrounding the plurality of fins;
- an integrated body diode surrounding the plurality of fins;
- and
- an isolation region disposed between the plurality of fins and the integrated body diode.
4 more elements
Dependencies are inferred from the claim text.