Semiconductor device

A semiconductor device, comprising:

• a substrate;
• a channel pattern on the substrate, the channel pattern including a first semiconductor pattern, a second semiconductor pattern and a third semiconductor pattern sequentially stacked on the substrate;
• a first source/drain pattern and a second source/drain pattern that are on the substrate, the channel pattern being between the first and second source/drain patterns;
• a gate electrode on the channel pattern, the gate electrode including a first portion between the substrate and the first semiconductor pattern, a second portion between the first semiconductor pattern and the second semiconductor pattern, and a third portion between the second semiconductor pattern and the third semiconductor pattern;
• a first barrier insulating pattern between the first portion and the first source/drain pattern;
• and
• a second barrier insulating pattern between the first portion and the second source/drain pattern,
• wherein the first barrier insulating pattern includes a first sidewall in contact with the first source/drain pattern,
• wherein the second barrier insulating pattern includes a second sidewall in contact with the second source/drain pattern, and
• wherein a first distance between the first sidewall and the second sidewall increases with decreasing distance from a bottom surface of the substrate.

A semiconductor device, comprising:

• a substrate including a PMOSFET region;
• a channel pattern on the PMOSFET region, the channel pattern including a first semiconductor pattern, a second semiconductor pattern and a third semiconductor pattern sequentially stacked on the substrate;
• a source/drain pattern on the PMOSFET region and connected to the channel pattern;
• and
• a gate electrode on the channel pattern, the gate electrode including a first portion between the substrate and the first semiconductor pattern, a second portion between the first semiconductor pattern and the second semiconductor pattern, and a third portion between the second semiconductor pattern and the third semiconductor pattern,
• wherein a width of the first portion increases with decreasing distance from a bottom surface of the substrate.