Metal gate patterning process including dielectric Fin formation

A method comprising,

• forming a first stack of semiconductor layers extending from a substrate, wherein there is a first distance between adjacent semiconductor layers of the first stack of semiconductor layers;
• forming a dielectric fin extending from the substrate, wherein the first stack of semiconductor layers is adjacent a first sidewall of the dielectric fin, and wherein there is a second distance between an end of a semiconductor layer of the first stack of semiconductor layers and the first sidewall of the dielectric fin;
• forming a second stack of semiconductor layers extending from the substrate and adjacent a second sidewall of the dielectric fin, the second sidewall opposing the first sidewall, wherein there is the first distance between adjacent semiconductor layers of the second stack of semiconductor layers;
• and
• depositing a metal layer over the first stack of semiconductor layers, the second stack of semiconductor layers, and the dielectric fin, and
• wherein the metal layer is a first metal layer, and wherein the method further comprises:
• forming a second metal layer over the first metal layer;
• depositing a mask over the second metal layer;
• etching the mask over the first stack of semiconductor layers to expose the second metal layer over the first stack of semiconductor layers;
• and
• etching the second metal layer to expose the first metal layer over the first stack of semiconductor layers.

A method comprising:

• forming a fin structure on a substrate, wherein the fin structure includes a first semiconductor layer and a second semiconductor layer spaced apart from the first semiconductor layer such that a first portion of an air gap extends a first distance from a bottom surface of the second semiconductor layer to a top surface of the first semiconductor layer after the forming of the fin structure on the substrate;
• forming a dielectric structure that includes a dielectric fin on the substrate, wherein the dielectric structure has a sidewall facing a sidewall of each of the first and second semiconductor layers such that a second portion of the air gap extends a second distance from each of the first and second semiconductor layers to the sidewall of the dielectric structure, the second distance being greater than the first distance, wherein the dielectric structure includes a sidewall spacer disposed on the dielectric fin and wherein the sidewall of the dielectric structure is defined by the sidewall spacer;
• forming a dielectric layer in the first portion of the air gap around each of the first and second semiconductor layers such that the dielectric layer is disposed on the bottom surface of the second semiconductor layer and the top surface of the first semiconductor layer, wherein the forming of the dielectric layer in the first portion of the air gap includes forming the dielectric layer directly on the sidewall spacer;
• and
• forming a metal layer in the first portion of the air gap on the dielectric layer and in the second portion of the air gap on the sidewall of the dielectric fin, wherein the first portion of the air gap is completely filled by the dielectric layer and the metal layer and the second portion of the air gap includes an unoccupied portion after the forming of the metal layer.