Piezo-resistive transistor based resonator with ferroelectric gate dielectric

An apparatus comprising:

• a first interconnect comprising metal, wherein the first interconnect is on a first layer;
• a second interconnect comprising metal, wherein the second interconnect is on the first layer and is parallel to the first interconnect, wherein the first and second interconnect are not coupled to one another;
• a first transistor comprising a first fin comprising first source and drain regions, and a first channel between the first source and drain regions;
• a second transistor comprising a second fin comprising second source and drain regions, and a second channel between the second source and drain regions;
• a gate on the first fin between the first source and drain regions and on the second fin between the second source and drain regions, wherein the first and second transistors and the gate are positioned in a backend of the apparatus;
• a third interconnect comprising metal, wherein the third interconnect is on a second layer;
• and
• a fourth interconnect comprising metal, wherein the fourth interconnect is on the second layer and is parallel to the third interconnect, wherein the third and fourth interconnects are not coupled to one another,
• wherein the gate comprises a ferroelectric (FE) gate dielectric,
• wherein the first and second interconnects are above the first and second transistors and the gate, and
• wherein the third and fourth interconnects are below the first and second transistors and the gate.