Double control gate semi-floating gate transistor and method for preparing the same

A double control gate semi-floating gate transistor, wherein the double control gate semi-floating gate transistor at least comprises:

• a substrate 200 and a lightly doped well region 201 on the substrate, the lightly doped well region being provided with a U-shaped groove 203, a bottom of the U-shaped groove being located on an upper surface of the substrate;
• a floating gate stack, the floating gate stack comprising a floating gate oxide layer 204 and a floating gate polysilicon layer 206, one part of the floating gate oxide layer 204 covering sidewalls and the bottom of the U-shaped groove 203, the other part covering an upper surface of the lightly doped well region 201 on one side of the U-shaped groove, the floating gate oxide layer 204 covering the upper surface of the lightly doped well region 201 being provided with an opening 205 for exposing the upper surface of the lightly doped well region 201, the floating gate polysilicon layer 206 being filled in the U-shaped groove and covering the floating gate oxide layer 204 and the opening 205, the floating gate polysilicon layer 206 being in contact with the upper surface of the lightly doped well region 201 by covering the opening 205;
• a polysilicon control gate stack, the polysilicon control gate stack comprising a polysilicon control gate oxide layer 207 on the floating gate polysilicon layer 206 and a polysilicon control gate polysilicon layer 208 on the polysilicon control gate oxide layer 207;
• a metal control gate stack, the metal control gate stack comprising a high-K dielectric layer 209 and a metal gate 210 on the high-K dielectric layer 209, the metal control gate stack continuously covering a part of the polysilicon control gate polysilicon layer 208 and the lightly doped well region 201, an upper surface of the metal gate 210 being higher than an upper surface of the polysilicon control gate polysilicon layer 208, wherein a height difference between the upper surface of the metal gate 210 and the upper surface of the polysilicon control gate polysilicon layer 208 is 0.1-50 nm;
• sidewalls 211 formed on sidewalls of the metal gate 210 and outer sides of the floating gate stack and the polysilicon control gate stack;
• and
• source and drain regions, the source and drain regions being respectively located in the lightly doped well region 201 on outer sides of the floating gate stack, the polysilicon control gate stack and the metal control gate stack.