Transistor gate structures and methods of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsin-Yi Lee, Cheng-Lung Hung, Chi On Chui
Life of this patent
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Abstract
In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a p-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a n-type work function metal, the n-type work function metal different from the p-type work function metal; and a fill layer on the second work function tuning layer.
Claims20
A device comprising:
- nanostructures;
- a gate dielectric layer on the nanostructures;
- a first work function tuning layer on the gate dielectric layer, the first work function tuning layer comprising a p-type work function metal, the first work function tuning layer and the gate dielectric layer completely filling a region between the nanostructures;
- a barrier layer on the first work function tuning layer;
- a second work function tuning layer on the barrier layer, the second work function tuning layer comprising a n-type work function metal, the n-type work function metal different from the p-type work function metal;
- and
- a fill layer on the second work function tuning layer.
A device comprising:
- a first transistor comprising:
- a first channel region;
- a first gate dielectric layer on the first channel region;
- a p-type work function tuning layer on the first gate dielectric layer;
- a barrier layer on the p-type work function tuning layer;
- a first n-type work function tuning layer on the barrier layer, the first n-type work function tuning layer comprising a metal, an upper portion of the barrier layer comprising residue of the metal at a greater concentration than a lower portion of the barrier layer, the upper portion of the barrier layer proximate the first n-type work function tuning layer, the lower portion of the barrier layer proximate the p-type work function tuning layer;
- and
- a first fill layer on the first n-type work function tuning layer;
- and
- a second transistor comprising:
- a second channel region;
- a second gate dielectric layer on the second channel region;
- a second n-type work function tuning layer on the second gate dielectric layer, the second n-type work function tuning layer comprising a material, the material comprising the metal;
- a glue layer on the second n-type work function tuning layer, the material of the second n-type work function tuning layer extending continuously between the second gate dielectric layer and the glue layer;
- and
- a second fill layer on the glue layer.
A method comprising:
- depositing a gate dielectric layer having a first portion and a second portion, the first portion deposited on a first channel region, the second portion deposited on a second channel region;
- depositing a first work function tuning layer on the first portion and the second portion of the gate dielectric layer;
- depositing a barrier layer on the first work function tuning layer;
- removing portions of the barrier layer and the first work function tuning layer to expose the second portion of the gate dielectric layer;
- and
- depositing a second work function tuning layer on the barrier layer and the second portion of the gate dielectric layer, the barrier layer inhibiting modification of a first work function of the first work function tuning layer during deposition of the second work function tuning layer.
Dependencies are inferred from the claim text.