Semiconductor device

A semiconductor device of chip-size package type that is face-down mountable, the semiconductor device comprising:

• a semiconductor substrate that comprises silicon and contains an impurity of a first conductivity type;
• a low-concentration impurity layer on and in contact with the semiconductor substrate, the low-concentration impurity layer containing an impurity of the first conductivity type having a concentration lower than a concentration of the impurity of the first conductivity type in the semiconductor substrate;
• and
• a vertical field effect transistor including:
• a body region of a second conductivity type in a surface of the low-concentration impurity layer, the second conductivity type being different from the first conductivity type;
• source regions of the first conductivity type in a surface of the body region;
• a source electrode electrically connected to the source regions;
• a plurality of trenches extending in a first direction parallel to a top surface of the semiconductor substrate and aligned at regular intervals in a second direction orthogonal to the first direction, each of the plurality of trenches having a depth penetrating the body region from a top surface of the low-concentration impurity layer and not reaching a bottom of the low-concentration impurity layer;
• gate insulating films, each of which covers at least a portion of a surface of a corresponding trench among the plurality of trenches;
• gate conductors, each of which is disposed on a corresponding gate insulating film among the gate insulating films;
• and
• connection portions that electrically connect the body region and the source electrode, wherein
• the source regions and the connection portions are alternately and cyclically disposed in the first direction in the vertical field effect transistor,
• Lxm≤Lxr≤0.20 μm holds true where Lxm [μm] denotes a trench-to-trench distance between adjacent trenches that are adjacent to each other in the second direction among the plurality of trenches, and Lxr [μm] denotes an inner width of one trench among the plurality of trenches, and
• the following formulas hold true:
• LB<0.35 μm;
• and
• LS≤0.12×Vss×Lxm−0.76×Lxm−0.05×Vss+1.26 [μm], where LB [μm] denotes a length, in the first direction, of one connection portion among the connection portions, LS [μm] denotes a length, in the first direction, of one source region among the source regions, and Vss [V] denotes a maximum specification voltage of the vertical field effect transistor.