Three-dimensional (3D) semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsJunhyoung Kim, Geunwon Lim, Manjoong Kim
Life of this patent
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Abstract
A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.
Claims20
A three-dimensional (3D) semiconductor memory device comprising:
- a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions;
- and
- a first block structure on the substrate, the first block structure having a first edge,
- wherein the first block structure has a first width on the cell array region,
- wherein the first block structure has a second width on the first connection region,
- wherein the first block structure has a third width on the second connection region,
- wherein the first width, the second width and the third width are parallel to a second direction intersecting the first direction and each of the first, second, and third widths extend from the first edge towards an edge opposite the first edge, and
- wherein the first width is less than the second width and is greater than the third width.
A three-dimensional (3D) semiconductor memory device comprising:
- a first block structure, a second block structure and a third block structure, on a substrate and are spaced apart from each other in a first direction;
- a first block separation region separating the first block structure and the second block structure from each other;
- and
- a second block separation region separating the second block structure and the third block structure from each other,
- wherein the first block separation region is spaced apart from the second block separation region, and
- wherein at least one of the first block separation region or the second block separation region has a staircase shape when viewed in a plan view.
A three-dimensional (3D) semiconductor memory device comprising:
- a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions;
- and
- a first block structure disposed on the substrate,
- wherein the first block structure comprises:
- first lower electrodes at a lowermost position;
- and first upper electrodes at an uppermost position,
- wherein the first upper electrodes are spaced apart from each other in a second direction intersecting the first direction and have line shapes extending in the first direction,
- wherein each of the first upper electrodes has a first width parallel to the second direction,
- wherein the first lower electrodes are spaced apart from each other in the second direction intersecting the first direction,
- wherein each of the first lower electrode includes a protrusion laterally protruding from a sidewall of an outermost one of the first upper electrodes on one of the first and second connection regions,
- wherein each of the protrusions have a second width parallel to the second direction, and
- wherein the second width ranges from one to three times the first width, the second width of each of the protrusions decreasing from a lowermost first lower electrode to an uppermost first lower electrode.
Dependencies are inferred from the claim text.