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US 11,637,117 B2Granted
Semiconductor device having selection line stud connected to string selection line
AssigneeSamsung Electronics Co., Ltd.
InventorsHyojoon Ryu, Kwanyong Kim, Seogoo Kang, Sunil Shim, Wonseok Cho, Jeehon Han
Life of this patent
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Abstract
A semiconductor device includes; a memory stack disposed on a substrate and including a lower gate electrode, an upper gate stack including a string selection line, a vertically extending memory gate contact disposed on the lower gate electrode, and a vertically extending selection line stud disposed on the string selection line. The string selection line includes a material different from that of the lower gate electrode, and the selection line stud includes a material different from that of the memory gate contact.
Claims20
A semiconductor device comprising:
- a memory stack disposed on a substrate, the memory stack including a lower gate electrode;
- a channel structure vertically penetrating the memory stack;
- an upper gate stack disposed on the memory stack, the upper gate stack including a string selection line;
- a channel contact vertically penetrating the upper gate stack and connected to the channel structure;
- a vertically extending memory gate contact contacting the lower gate electrode;
- a vertically extending lower stud disposed on a top surface of the memory gate contact;
- and
- a vertically extending selection line stud disposed on the string selection line,
- wherein the string selection line includes a material different from a material of the lower gate electrode,
- the selection line stud is a contiguous stud having a bottom surface on the string selection line and a top surface, and
- the top surface of the selection line stud is disposed at a same level as a top surface of the lower stud.
8 more elements
A semiconductor device comprising:
- a memory stack including lower gate electrodes spaced apart from each other in a vertical direction;
- a first channel structure vertically penetrating the memory stack and including a first channel layer;
- an upper gate electrode disposed on the memory stack;
- a second channel structure vertically penetrating the upper gate electrode, connected to the first channel structure, and including a second channel layer;
- lower gate contacts contacting the lower gate electrodes;
- lower gate studs on and contacting the lower gate contacts;
- an upper gate stud on and contacting the upper gate electrode;
- and
- a channel stud on and contacting the second channel structure,
- wherein the upper gate electrode includes a material different from a material of the lower gate electrodes,
- wherein the upper gate stud is contiguous stud having a bottom surface contacting the upper gate electrode and a top surface, and
- wherein the top surface of the upper gate stud is at a higher level than a top surface of each of the lower gate contacts.
9 more elements
A semiconductor device comprising:
- a substrate including a common source;
- a memory stack on the substrate, the memory stack including lower interlayer insulating layers and lower gate electrodes alternately stacked in a vertical direction;
- a first channel structure penetrating through the memory stack;
- an upper gate electrode on the memory stack;
- a second channel structure vertically penetrating the upper gate electrode, connected to the first channel structure;
- lower gate contacts contacting the lower gate electrodes;
- an upper gate stud on and contacting the upper gate electrode;
- and
- a channel stud on and contacting the second channel structure,
- wherein the upper gate electrode includes a material different from a material of the lower gate electrodes,
- wherein the first channel structure includes
- a first buried insulating pattern, and
- a first channel layer at least on at least a side surface of the first buried insulating pattern and contacting the common source,
- wherein the second channel structure includes
- a second buried insulating pattern, and
- a second channel layer on a side surface of the second buried insulating pattern and a bottom surface of the second buried insulating pattern,
- wherein the second buried insulating pattern is spaced apart from the first buried insulating pattern, and
- wherein a top surface of each of the lower gate contacts is at a different level than a top surface of the channel stud and a top surface of the upper gate stud.
15 more elements
Dependencies are inferred from the claim text.