Semiconductor memory device

A semiconductor memory device comprising:

• a memory string extending in a first direction perpendicular to a substrate, the memory string having a first select transistor and memory cell transistors connected in series;
• electrodes stacked in the first direction, the electrodes having a first select electrode connected to the first select transistor and control electrodes connected to the memory cell transistors;
• a first length between the memory string and a first edge of the first select electrode in a second direction crossing the first direction that is smaller than a second length between the memory string and a second edge of one of the control electrodes in the second direction;
• a first slit extending in the first direction and the second direction in a memory cell area and dividing the first select electrode in a third direction crossing the first direction and the second direction, a bottom of the first slit being under the one of the control electrodes and a third edge of the first slit being between the first edge and the second edge in the second direction;
• and
• a second slit extending in the first direction and the second direction in a contact area without dividing the first select electrode in the third direction, a fifth edge of the second slit being between the first edge and the second edge.