Vertical non-volatile memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsYounghwan Son, Boyoung Lee, Seoungwon Lee, Seunghwan Lee
Life of this patent
Estimating the term…
Abstract
A vertical non-volatile memory device includes a stack body including gate patterns and interlayer insulating patterns stacked in a stacking direction, the stack body having a through hole, which extends in the stacking direction, in the gate patterns and in the interlayer insulating patterns; a semiconductor pillar in the through hole and extending in the stacking direction; data storage structures between the gate patterns and the semiconductor pillar in the through hole, the data storage structures including charge storage layers; and dummy charge storage layers on a sidewall of the interlayer insulating patterns toward the semiconductor pillar in the through hole.
Claims19
A vertical non-volatile memory device, comprising:
- a stack body including gate patterns and interlayer insulating patterns stacked in a stacking direction, the stack body having a through hole, which extends in the stacking direction, in the gate patterns and in the interlayer insulating patterns;
- a semiconductor pillar in the through hole and extending in the stacking direction;
- data storage structures between the gate patterns and the semiconductor pillar in the through hole, the data storage structures including charge storage layers;
- and
- dummy charge storage layers on a sidewall of the interlayer insulating patterns toward the semiconductor pillar in the through hole, the dummy charge storage layers being formed of a same charge storage material as the charge storage layers.
A vertical non-volatile memory device, comprising:
- a stack body including gate patterns and interlayer insulating patterns that are alternately stacked in a stacking direction, the stack body having a through hole extending in the stacking direction in the gate patterns and the interlayer insulating patterns, the stack body including recess holes communicating with the through hole and recessed from a sidewall of the interlayer insulating patterns in a direction of the gate patterns;
- data storage structures including blocking insulating layers in contact with the gate patterns in the recess holes, charge storage layers in contact with the blocking insulating layers in the recess holes, and a tunnel insulating layer in contact with the charge storage layers and extending in the stacking direction in the through hole;
- a semiconductor pillar in contact with the data storage structures and extending in the stacking direction in the through hole and the recess holes;
- dummy charge storage layers on a sidewall of the interlayer insulating patterns toward the semiconductor pillar in the through hole;
- and
- isolated insulating layers arranged in the stacking direction and in contact with the charge storage layers in the recess holes and the through hole, wherein the charge storage layers are separated from the dummy charge storage layers by the isolated insulating layers.
A vertical non-volatile memory device, comprising:
- a stack body including gate patterns and interlayer insulating patterns that are alternately stacked, the stack body having a through hole extending in a stacking direction in the gate patterns and the interlayer insulating patterns, the stack body including curved-surface recess holes that are recessed from a sidewall of the interlayer insulating patterns in a direction of the gate patterns, the curved-surface recess holes communicating with the through hole and having a curved surface;
- curved-surface data storage structures in the curved-surface recess holes, the curved-surface data storage structures including curved-surface blocking insulating layers in contact with the gate patterns, curved-surface charge storage layers in contact with the curved-surface blocking insulating layers, and a curved-surface tunnel insulating layer in contact with the curved-surface charge storage layers in the curved-type recess holes and extending in the stacking direction in the through hole;
- isolated insulating layers in the stacking direction in the curved-surface recess holes and the through hole to contact the curved-surface charge storage layers;
- dummy charge storage layers on the sidewall of the interlayer insulating patterns in the through hole and the curved-surface recess holes, the dummy charge storage layers being separated by the isolated insulating layers;
- and
- a curved-surface semiconductor pillar being on a sidewall of the curved-surface tunnel insulating layer and a side of the dummy charge storage layers and extending in the stacking direction in the through hole.
Dependencies are inferred from the claim text.