Non-volatile memory device and method for manufacturing the same
AssigneeWinbond Electronics Corp.
InventorsChun-Hao Chen, Wei-Kuang Chung
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AssigneeWinbond Electronics Corp.
InventorsChun-Hao Chen, Wei-Kuang Chung
Estimating the term…
A non-volatile memory device and its manufacturing method are provided. The non-volatile memory device includes a substrate and a plurality of first gate structures and a plurality of second gate structures formed on the substrate. The substrate includes a center region and two border regions located on opposite sides of the center region. The center region and two border regions are located in an array region. The first gate structures are located in the center region, and the second gate structures are located in one of the border regions. Each of the first gate structures has a first width, and each of the second gate structures has a second width less than the first width. There is a first spacing between the first gate structures, and there is a second spacing which is greater than the first spacing between the second gate structures.
A non-volatile memory device, comprising:
A method for manufacturing a non-volatile memory device, comprising:
The method for manufacturing the non-volatile memory device as claimed in claim V, wherein defining the center region and the border regions on the substrate further comprises defining two middle regions on the substrate, wherein each of the middle regions is located between the center region and one of the border regions, and the method for manufacturing the non-volatile memory device further comprises:
Dependencies are inferred from the claim text.
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Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the boundary region between the core…
Of FETs having insulated gates [IGFET]: of FETs having floating gates
About 14 years 4 months of term left · ends 3 Mar 2041 (estimated)
This Application claims priority of Taiwan Patent Application No. 109107213, filed on Mar. 5, 2020, the entirety of which is incorporated by reference herein.
The present disclosure relates to a memory device, and in particular, it relates to a non-volatile memory device and a method for manufacturing the same.
Manufacturing processes have evolved toward miniaturization. In existing flash memory, the contact structure between the gate structures usually has a high aspect ratio, which causes a problem of high contact resistance. In the worst case, such contact structure with high aspect ratio may not be electrically connected to the substrate, thereby causing the failure of the flash memory. As a result, the yield of the flash memory will be reduced. In addition, as the spacing between the gate structures becomes smaller, the uniformity of these contact structures becomes difficult to control, thereby resulting in a non-uniform erasing ability of the memory cells of the flash memory. In order to avoid the above-mentioned problems, the spacing between the gate structures is increased by reducing the width of each gate structure in the memory array. However, as the width of the gate structure is reduced, it will cause a problem of reduced data retention ability and longer operation time. Therefore, how to reduce the contact resistance of the contact structure and improve the uniformity of the contact structures without significantly affecting the data retention ability and the operation time is a subject that the industry in this field is eager to improve.
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1 is a top-view of a non-volatile memory device in accordance with some embodiments.
FIG. 2 is a top-view of an array region in accordance with some embodiments.
The present disclosure is best understood from the following detailed description when read with the accompanying figures. The present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
In the disclosure, the term “about” or “approximately” means in a range of 20% of a given value or range, preferably 10%, and more preferably 5%. In the disclosure, if there is no specific explanation, a given value or range means an approximate value which may imply the meaning of “about” or “approximately”. In this specification, “X is equal to or similar to Y” means that the absolute value of the difference between the two is within 5.0% of the larger one.
The embodiments of the present invention provides a non-volatile memory device and a method for manufacturing the same. FIG. 1 is a top-view of a non-volatile memory device 500 in accordance with some embodiments. FIG. 2 is a top-view of an array region 100 in accordance with some embodiments. In one embodiment, the non-volatile memory device is a NOR flash memory.