Semiconductor device

A semiconductor device, comprising:

• a substrate having first and second regions;
• a stack structure including gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate in the first region, and the gate electrodes extending in a second direction perpendicular to the first direction by different lengths and providing pad regions in the second region;
• separation regions penetrating through the stack structure and extending in the second direction in the first and second regions, and spaced apart from each other in the second direction in the second region;
• channel structures penetrating through the stack structure and extending perpendicularly to the substrate in the first region;
• and
• dummy channel structures penetrating through the stack structure and extending perpendicularly to the substrate in the second region,
• wherein the stack structure includes an upper pad region and a lower pad region, and each of the upper pad region and the lower pad region includes a region between the separation regions that are adjacent to each other in the second direction,
• wherein a number of the dummy channel structures penetrating through the upper pad region is different from a number of the dummy channel structures penetrating through the lower pad region,
• wherein a first gate electrode among the gate electrodes is exposed upwardly in the upper pad region, and
• wherein a second gate electrode among the gate electrodes is exposed upwardly in the lower pad region.

A semiconductor device, comprising:

• a substrate having first and second regions;
• gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate on the first region, extending in a second direction perpendicular to the first direction by different lengths on the second region, and including at least one ground select gate electrode, memory cell gate electrodes, and at least one string select gate electrode stacked in order from the substrate;
• first separation regions penetrating through the gate electrodes and extending in the second direction in the first and second regions, and spaced apart from each other in a third direction perpendicular to the first and second directions;
• second separation regions penetrating through the gate electrodes and extending in the second direction between the first separation regions, and spaced apart from each other in the second direction in the second region;
• third separation regions penetrating through the gate electrodes and extending in the second direction between the first separation regions and the second separation regions, and spaced apart from each other in the second direction with spacing regions therebetween in the second region;
• a substrate insulating layer disposed in the substrate between the first separation regions and the second separation regions in the second region;
• channel structures penetrating through the gate electrodes and extending perpendicularly to the substrate in the first region;
• and
• dummy channel structures penetrating through the gate electrodes and the substrate insulating layer and extending perpendicularly in the second region,
• wherein a stack structure of the gate electrodes includes an upper region and a lower region disposed between a pair of the first separation regions and respectively including the spacing regions, and
• wherein a number of the dummy channel structures penetrating through the upper region is greater than a number of the dummy channel structures penetrating through the lower region.