Source/drain feature separation structure

A static random access memory (SRAM) cell, comprising:

• a pull-down transistor comprising a first source/drain feature;
• a pull-up transistor comprising a second source/drain feature;
• an isolation transistor comprising a third source/drain feature;
• a first dummy fin separating the pull-down transistor and the pull-up transistor along a direction;
• and
• a second dummy fin separating the second source/drain feature and the third source/drain feature,
• wherein the pull-up transistor is disposed between the first dummy fin and the second dummy fin along the direction,
• wherein the second source/drain feature is in physical contact with the first dummy fin and the second dummy fin,
• wherein the first dummy fin comprises an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed directly on top surfaces of the outer dielectric layer and the inner dielectric layer,
• wherein the second dummy fin comprises a bottom portion and a second capping layer disposed directly on a top surface of the bottom portion.

A semiconductor structure, comprising:

• a first source/drain feature;
• a second source/drain feature;
• a third source/drain feature;
• a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction;
• a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction;
• and
• a third dummy fin disposed adjacent to the third source/drain feature along the direction, such that the third source/drain feature is between the second dummy fin and the third dummy fin,
• wherein the first source/drain feature comprises silicon and an n-type dopant,
• wherein the second source/drain feature and the third source/drain feature comprise silicon germanium and a p-type dopant,
• wherein both a first width of the first dummy fin along the direction and a third width of the third dummy fin along the direction are greater than a second width of the second dummy fin along the direction,
• wherein a top surface of the first dummy fin, a top surface of the third dummy fin, and a top surface of the second dummy fin are coplanar,
• wherein the first dummy fin comprises a first dielectric layer as a first outer dielectric layer and a second dielectric layer as a first inner dielectric layer,
• wherein the second dummy fin comprises the first dielectric layer as a bottom portion and is free of the second dielectric layer,
• wherein the third dummy fin comprises the first dielectric layer as a second outer dielectric layer and the second dielectric layer as a second inner dielectric layer, and
• wherein the first dielectric layer is more etch resistant than the second dielectric layer.