Memory array circuit and method of manufacturing same

A method of forming a memory circuit, the method comprising:

• generating, by a processor, a layout design of the memory circuit, the layout design having a cell boundary, wherein the generating of the layout design comprises:
• generating a first active region layout pattern corresponding to fabricating a first active region of a first pull up transistor, the first active region layout pattern extending in a first direction, and being located on a first level;
• generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, the second active region layout pattern extending in the first direction, being located on the first level, and being separated from the first active region layout pattern in a second direction different from the first direction;
• and
• generating a first metal contact layout pattern corresponding to fabricating a first metal contact, the first metal contact layout pattern extending in the second direction, overlapping the cell boundary of the memory circuit and the first active region layout pattern, and being located on a second level different from the first level, and the first metal contact electrically coupled to a source of the first pull up transistor;
• and
• manufacturing the memory circuit based on the layout design, the memory circuit being a four transistor (4T) memory cell including at least the first pass gate transistor and the first pull up transistor.

A method of forming a memory circuit, the method comprising:

• generating, by a processor, a layout design of the memory circuit, wherein the generating of the layout design comprises:
• placing a first active region layout pattern on a first level, the first active region layout pattern corresponding to fabricating a first active region of a first pull up transistor, the first active region layout pattern extending in a first direction;
• placing a second active region layout pattern on the first level, the second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, the second active region layout pattern extending in the first direction, and being separated from the first active region layout pattern in a second direction different from the first direction;
• and
• placing a first metal contact layout pattern on a second level different from the first level, the first metal contact layout pattern corresponding to fabricating a first metal contact, the first metal contact layout pattern extending in the second direction, extending from the first active region layout pattern to the second active region layout pattern, and the first metal contact electrically coupling a drain of the first pull up transistor to a drain of the first pass gate transistor;
• and
• manufacturing the memory circuit based on the layout design, the memory circuit being a four transistor (4T) memory cell including at least the first pass gate transistor and the first pull up transistor.