Semiconductor memory devices including stacked transistors and methods of fabricating the same

A semiconductor memory device comprising:

• a bitline on a substrate, the bitline extending in a first direction that is perpendicular to a top surface of the substrate;
• a gate electrode including upper and lower gate electrodes and a plurality of connecting gate electrodes, wherein each of the upper and lower gate electrodes extends in a second direction that is parallel to the top surface of the substrate, and the plurality of connecting gate electrodes are arranged in the second direction, and wherein the upper gate electrode is spaced apart from the lower gate electrode in the first direction, and each of the plurality of connecting gate electrodes connects the upper and lower gate electrodes to each other;
• a semiconductor pattern between the lower and upper gate electrodes and between a pair of adjacent connecting gate electrodes of the plurality of connecting gate electrodes, the semiconductor pattern being electrically connected to the bitline;
• a vertical insulating structure between the pair of adjacent connecting gate electrodes, the vertical insulating structure extending through the upper and lower gate electrodes and the semiconductor pattern and extending in the first direction;
• and
• an information storage element electrically connected to the semiconductor pattern.

A semiconductor memory device comprising:

• a bitline on a substrate, the bitline extending in a first direction that is perpendicular to a top surface of the substrate;
• a semiconductor pattern on the substrate, the semiconductor pattern being electrically connected to the bitline and having a first loop shape;
• a gate electrode on the semiconductor pattern and extending in a second direction that is parallel to the top surface of the substrate;
• and
• an information storage element electrically connected to the semiconductor pattern,
• wherein the information storage element includes a first electrode electrically connected to the semiconductor pattern, a second electrode spaced apart from the first electrode, and a dielectric film between the first and second electrodes,
• the first electrode has a second loop shape, and
• the bitline, the semiconductor pattern and the information storage element are arranged along the second direction, and the semiconductor pattern is between the bitline and the information storage element.