Gate isolation for multigate device

A method comprising:

• forming a first fin and a second fin extending from a substrate, wherein:
• the first fin and the second fin each include a fin portion extending from the substrate and a semiconductor layer stack over the fin portion, wherein the semiconductor layer stack includes first semiconductor layers and second semiconductor layers, and
• a trench is between the first fin and the second fin, wherein the trench has a first sidewall formed by the first fin, a second sidewall formed by the second fin, and a bottom extending between the first sidewall and the second sidewall, wherein the bottom is formed by the substrate;
• forming a first dielectric feature that fills a lower portion of the trench, wherein the first dielectric feature is between the fin portion of the first fin and the fin portion of the second fin;
• forming a sacrificial semiconductor layer and a second dielectric feature that fill an upper portion of the trench, wherein:
• the sacrificial semiconductor layer and the second dielectric feature are between the semiconductor layer stack of the first fin and the semiconductor layer stack of the second fin, and
• the second dielectric feature includes a low-k dielectric layer disposed over a high-k dielectric layer,
• in a first region of the first fin and the second fin, replacing the first semiconductor layers and the sacrificial semiconductor layer with a first gate stack that surrounds the second semiconductor layers of the first fin and a second gate stack that surrounds the second semiconductor layers of the second fin, wherein the second dielectric feature separates the first gate stack and the second gate stack;
• and
• in a second region of the first fin and the second fin, replacing the first semiconductor layers, the second semiconductor layers, and the sacrificial semiconductor layer with a first epitaxial source/drain over the fin portion of the first fin and a second epitaxial source/drain over the fin portion of the second fin, wherein the second dielectric feature separates the first epitaxial source/drain and the second epitaxial source/drain.

A method comprising:

• forming an isolation feature over a substrate, wherein the isolation feature is between a first semiconductor fin and a second semiconductor fin extending from the substrate;
• forming a gate isolation fin over the isolation feature, wherein:
• a width of the gate isolation fin is less than a width of the isolation feature,
• the gate isolation fin is between the first semiconductor fin and the second semiconductor fin,
• the gate isolation fin includes a first dielectric layer and a second dielectric layer disposed over the first dielectric layer, and
• the first dielectric layer has a first dielectric constant, the second dielectric layer has a second dielectric constant, and the second dielectric constant is less than the first dielectric constant;
• and
• forming a first multigate device and a second multigate device from the first semiconductor fin and the second semiconductor fin, respectively, after forming the gate isolation fin, wherein the gate isolation fin separates a first metal gate of the first multigate device and a second metal gate of the second multigate device.