Semiconductor device and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWang-Chun Huang, Hou-Yu Chen, Kuan-Lun Cheng, Chih-Hao Wang
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWang-Chun Huang, Hou-Yu Chen, Kuan-Lun Cheng, Chih-Hao Wang
Estimating the term…
A semiconductor device includes a gate structure, a source/drain epitaxial structure, a front-side interconnection structure, a backside via, an isolation material, and a sidewall spacer. The source/drain epitaxial structure is on a side of the gate structure. The front-side interconnection structure is on a front-side of the source/drain epitaxial structure. The backside via is connected to a backside of the source/drain epitaxial structure. The isolation material is on a side of the backside via and in contact with the gate structure. The sidewall spacer is sandwiched between the backside via and the isolation material. A height of the isolation material is greater than a height of the sidewall spacer.
A semiconductor device, comprising:
A semiconductor device, comprising:
A method comprising:
Dependencies are inferred from the claim text.
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Nanowire, nanosheet or nanotube semiconductor bodies: oriented parallel to substrates
Of only field-effect components: of only insulated-gate FETs [IGFET]
Of FETs having stacked nanowire, nanosheet or nanoribbon channels: forming inner spacers between adjacent channels, e.g. changing their shapes or…
Of FETs having stacked nanowire, nanosheet or nanoribbon channels: forming source or drain electrodes wherein semiconductor bodies are replaced by…
About 14 years 9 months of term left · ends 2 Aug 2041 (estimated)
The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIGS. 1-20E illustrate a method for manufacturing a semiconductor device at various stages in accordance with some embodiments of the present disclosure.
FIG. 21A is a perspective view of a semiconductor device in accordance with some embodiments of the present disclosure.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As used herein, “around,” “about,” “approximately,” or “substantially” shall generally mean within 20 percent, or within 10 percent, or within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around,” “about,” “approximately,” or “substantially” can be inferred if not expressly stated.