Pin modification for standard cells

A computer system comprising:

• a memory configured to store instructions;
• and
• a processor, that when executing the instructions, is configured to perform operations for routing one or more standard cells with a plurality of pins, the operations comprising:
• routing an interconnect to a first pin of a first standard cell, wherein the interconnect comprises a via;
• inserting a spacing between the interconnect and a second pin of a second standard cell adjacent to the first standard cell;
• determining whether the spacing separates the second pin from the interconnect by a separation greater than a predetermined distance;
• and
• in response to the separation being less than the predetermined distance, modifying a dimension of the second pin such that the second pin is spaced at a greater distance from a boundary of the second standard cell than that of an original position of the second pin.

A non-transitory computer-readable medium having instructions stored thereon that, when executed by a computing device, cause the computing device to perform operations comprising:

• routing an interconnect to a first pin of a first standard cell, wherein the interconnect comprises a via;
• inserting a spacing between the interconnect and a second pin of a second standard cell adjacent to the first standard cell;
• determining whether the spacing separates the second pin from the interconnect by a separation greater than a predetermined distance;
• and
• in response to the separation being less than the predetermined distance, modifying a dimension of the second pin such that the second pin is spaced at a greater distance from a boundary of the second standard cell than that of an original position of the second pin, wherein at least one of the routing, inserting, and modifying is performed by a processor.