Three-dimensional semiconductor memory device

A three-dimensional semiconductor memory device comprising:

• a cell wafer including a source plate, a first memory block including a plurality of first cell strings, which extend in a vertical direction from a bottom surface of the source plate, a second memory block including a plurality of second cell strings, which extend in the vertical direction from a top surface of the source plate, a plurality of first bit lines that are coupled to the plurality of first cell strings, and a plurality of second bit lines that are coupled to the plurality of second cell strings;
• a first peripheral wafer bonded to a bottom surface of the cell wafer, and including a first row decoder unit, which transfers an operating voltage to the first memory block;
• a second peripheral wafer bonded to a top surface of the cell wafer, and including a second row decoder unit, which transfers an operating voltage to the second memory block, and a page buffer circuit including a plurality of page buffers, wherein each of the plurality of page buffers is coupled in common to one of the plurality of first bit lines and one of the plurality of second bit lines;
• and
• a plurality of vertical contact structures coupled to the plurality of first bit lines, respectively, and passing through the plurality of first word lines, the source plate and the plurality of second word lines,
• wherein the plurality of first bit lines are coupled to the plurality of second bit lines, respectively, through the plurality of vertical contact structures,
• wherein the first memory block and the second memory block are configured to be erased independently of each other.

A three-dimensional semiconductor memory device comprising:

• a cell wafer including a source plate, a first sub memory cell array that is disposed under the source plate, and a second sub memory cell array that is disposed on the source plate;
• a first peripheral wafer bonded to a bottom surface of the cell wafer, and including a first logic circuit unit, which transfers an operating voltage to the first sub memory cell array;
• and
• a second peripheral wafer bonded to a top surface of the cell wafer, and including a second logic circuit unit, which transfers an operating voltage to the second sub memory cell array,
• wherein cell wafer and first and second peripheral wafers are each divided into a cell region and a slimming region SR, and the first sub memory cell array and the second sub memory cell array are disposed in the cell region, and the first logic circuit unit and the second logic circuit unit are disposed in the slimming region, and
• the cell region and the slimming region are arranged to minimize a delay of an operating voltage provided from the first logic circuit unit to the first sub memory cell array.