Semiconductor package including stacked semiconductor chips

A semiconductor package comprising:

• a base layer;
• a first semiconductor chip disposed over and spaced apart from the base layer;
• a semiconductor chip stack disposed between the base layer and the first semiconductor chip, the semiconductor chip stack including a plurality of second semiconductor chips that are stacked in a vertical direction;
• a first bridge die stack disposed between the base layer and the first semiconductor chip and disposed to be spaced apart from the semiconductor chip stack, the first bridge die stack including a plurality of first bridge dies that are stacked in the vertical direction and electrically connecting the first semiconductor chip and the base layer to supply power;
• and
• a second bridge die stack disposed between the base layer and the first semiconductor chip and disposed to be spaced apart from the semiconductor chip stack and the first bridge die stack, the second bridge die stack including a plurality of second bridge dies that are stacked in the vertical direction and electrically connecting the first semiconductor chip and the base layer to transmit a signal,
• wherein the first bridge die stack and the second bridge die stack are different from each other.

A semiconductor package comprising:

• a base layer;
• a first semiconductor chip disposed over and spaced apart from the base layer;
• a semiconductor chip stack disposed between the base layer and the first semiconductor chip, the semiconductor chip stack including a plurality of second semiconductor chips that are stacked in a vertical direction;
• a plurality of first interconnectors disposed between the base layer and the first semiconductor chip and disposed to be spaced apart from the semiconductor chip stack, the first interconnector electrically connecting the first semiconductor chip and the base layer and
• a plurality of second interconnectors disposed between the base layer and the first semiconductor chip and disposed to be spaced apart from the semiconductor chip stack and the plurality of first interconnectors, the plurality of second interconnectors electrically connecting the first semiconductor chip and the base layer,
• wherein each of the plurality of first interconnectors includes a plurality of conductive pillars that are stacked in the vertical direction,
• wherein at least one of a horizontal width and a horizontal pitch of each of the conductive pillars is greater than that of each of the plurality of second interconnectors.