US 11,637,076 B2 · Electrically isolated gate contact in FINFET technology for camouflaging integrated circuits from reverse engineering

Abstract

A system and method for adding a source contact, a drain contact, and an apparent gate contact to a FinFET having a fin including a source region, a drain region, and a gate disposed over the fin forming one or more transistor junctions with the fin. The method comprises producing a source contact opening extending downward to a first region electrically coupled to the source region, a drain contact opening extending downward to a second region electrically coupled to the drain region, and a gate contact opening extending downward to a third region electrically isolated from the gate, and filling the source contact opening, the drain contact opening, and the gate contact opening with a conductive metal.

Claims19

Dependent claims

A method of adding a source contact, a drain contact, and an apparent gate contact to a FinFET having a fin including a source region, a drain region, and a gate disposed over the fin forming one or more transistor junctions with the fin, comprising:

producing a source contact opening extending downward to a first region electrically coupled to the source region, a drain contact opening extending downward to a second region electrically coupled to the drain region, and a gate contact opening extending downward to a third region electrically isolated from the gate;
and
filling the source contact opening, the drain contact opening, and the gate contact opening with a conductive metal.

A camouflaged application specific integrated circuit (ASIC), comprising:

a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, the plurality of interconnected functional logic cells comprising:
at least one camouflaged FinFET, comprising:
a fin, having:
a source region;
a drain region;
a gate, substantially perpendicular to the fin, the gate forming one or more transistor junctions with the fin;
a source contact disposed in a source contact opening extending downward to a first region electrically coupled to the source region;
a drain contact disposed in a drain contact opening extending downward to a second region electrically coupled to the drain region;
and
a gate contact disposed in a gate contact opening extending downward to a third region electrically isolated from the gate.

7 more elements

A FinFET, comprising a fin including a source region, a drain region, and a gate disposed over the fin forming one or more transistor junctions with the fin, the FinFET having a source contact, a drain contact, and an apparent gate contact added by a method of performing operations comprising:

producing a source contact opening extending downward to a first region electrically coupled to the source region, a drain contact opening extending downward to a second region electrically coupled to the drain region, and a gate contact opening extending downward to a third region electrically isolated from the gate;
and
filling the source contact opening, the drain contact opening, and the gate contact opening with a conductive metal.

Dependencies are inferred from the claim text.

Facts

Application

17/157,567Filed 25 Jan 2021 · us provisional application

Priority

28 Jan 2020

Published

US 2021/0249363 A112 Aug 2021

Granted

25 Apr 2023

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 84/853
Complementary IGFETs, e.g. CMOS: comprising FinFETs
H10W 42/40
Arrangements for protection of devices: protecting against tampering, e.g. unauthorised inspection or reverse engineering
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/6219
Fin field-effect transistors [FinFET]: characterised by the source or drain electrodes

Electrically isolated gate contact in FINFET technology for camouflaging integrated circuits from reverse engineering

Life of this patent

Electrically isolated gate contact in FINFET technology for camouflaging integrated circuits from reverse engineering

Life of this patent

Abstract

Claims19