Method of fabricating a semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsHae-Jung Yu, Kyung Suk Oh
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.
Claims18
A method of fabricating a semiconductor package, the method comprising:
- providing a semiconductor chip;
- forming a redistribution substrate having a first surface and a second surface opposite to each other, the redistribution substrate including a plurality of first pads and a plurality of second pads on the first surface thereof;
- and
- fabricating a package including a plurality of conductive structures, the redistribution substrate, the semiconductor chip, and a plurality of external connection terminals,
- wherein the semiconductor chip and the plurality of conductive structures are disposed on the second surface of the redistribution substrate, the plurality of conductive structures spaced apart from the semiconductor chip,
- wherein the plurality of external connection terminals are provided on the plurality of conductive structures and electrically connected to the plurality of conductive structures, the plurality of external connection terminals having a non-overlapping relationship with respect to the semiconductor chip, in a top view,
- wherein the redistribution substrate has a first region and a second region spaced apart from each other in a plan view,
- wherein the plurality of first pads are provided on the first region of the redistribution substrate,
- wherein the plurality of second pads are provided on the second region of the redistribution substrate, the plurality of second pads and the plurality of first pads being electrically connected to the semiconductor chip, and the plurality of second pads having a second pitch different from a first pitch of the plurality of first pads, and
- wherein the first pitch is smaller than a pitch of the plurality of external connection terminals.
A method of fabricating a semiconductor package, the method comprising:
- providing a preliminary package including a first semiconductor chip, a plurality of conductive structures, and a molding pattern, such that a plurality of chip pads of the first semiconductor chip are exposed on a first surface of the preliminary package, and the plurality of conductive structures is spaced apart from the first semiconductor chip;
- forming a first redistribution layer on the first surface of the preliminary package;
- and
- forming a plurality of external connection terminals on a second surface of the preliminary package, the second surface being opposite to the first surface, and the plurality of external connection terminals being coupled to the plurality of conductive structures,
- wherein the first redistribution layer includes a redistribution pattern and a plurality of first redistribution pads coupled to the redistribution pattern, the redistribution pattern being coupled to the plurality of chip pads, and
- wherein the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.
A method of fabricating a semiconductor package, the method comprising:
- forming a redistribution layer by forming an insulation pattern on a carrier substrate and forming a redistribution pattern on the insulation pattern;
- forming a plurality of first redistribution pads and a plurality of second redistribution pads on a first surface of the redistribution layer, the plurality of first redistribution pads having a smaller pitch than a pitch of the plurality of second redistribution pads;
- coupling the plurality of first redistribution pads to the redistribution pattern of the redistribution layer;
- mounting a semiconductor chip on a second surface of the redistribution layer and electrically connecting the semiconductor chip to the redistribution layer;
- forming a plurality of conductive structures on the second surface of the redistribution layer and electrically connecting the plurality of conductive structures to the redistribution layer;
- and
- forming a plurality of external connection terminals on the plurality of conductive structures, such that the plurality of external connection terminals has a pitch greater than a pitch of the plurality of first redistribution pads,
- wherein the plurality of first redistribution pads are vertically overlapped with the plurality of conductive structures and are not vertically overlapped with the semiconductor chip.
Dependencies are inferred from the claim text.