Integrated circuit and method for forming the same

An integrated circuit, comprising:

• a first strip structure;
• a second strip structure;
• an isolation structure between the first strip structure and the second strip structure;
• a backside via in the isolation structure;
• a first epitaxy structure over the first strip structure;
• a second epitaxy structures over the second strip structure;
• a first contact over the first epitaxy structure, wherein a first portion of the first contact extends along a sidewall of the first epitaxy structure;
• and
• a second contact over the second epitaxy structure, wherein a bottommost position of the first portion of the first contact is below a bottommost position of the second contact.

A method, comprising:

• patterning a substrate to define a semiconductor strip over the substrate;
• depositing a dielectric liner over the semiconductor strip;
• depositing a conductive material over the dielectric liner;
• etching the conductive material, wherein the semiconductor strip protrudes from the etched conductive material;
• depositing a dielectric material over the conductive material and the dielectric liner;
• etching the dielectric material and the dielectric liner to define an isolation structure having a top surface lower than a top surface of the semiconductor strip;
• forming a source/drain epitaxy structure over the semiconductor strip;
• forming a dielectric layer surrounding the epitaxy structure;
• forming an interlayer dielectric layer over the epitaxy structure and the dielectric layer;
• etching the interlayer dielectric layer, the dielectric layer, and the isolation structure to define an opening exposing the conductive material;
• and
• forming a source/drain contact in the opening.