Interconnection structure and semiconductor package including the same

An interconnection structure, comprising:

• a dielectric layer;
• and
• a plurality of wiring patterns in the dielectric layer,
• wherein the plurality of wiring patterns include a first wiring pattern and a second wiring pattern that transmit signals independently from each other,
• wherein each of the first wiring pattern and the second wiring pattern includes:
• a via body;
• a via pad body that vertically overlaps the via body;
• and
• a line body that extends from the via pad body,
• wherein the via body, the via pad body, and the line body of a same one of the plurality of wiring patterns are integrally connected to each other,
• wherein a sidewall of the via body has a rounded shape, and
• wherein a level of a bottom surface of the via body included in the first wiring pattern is lower than a level of a bottom surface of the line body included in the second wiring pattern.

A semiconductor package, comprising:

• a redistribution substrate that includes a redistribution layer;
• a first semiconductor chip on one surface of the redistribution substrate;
• a plurality of chip pads on one surface of the first semiconductor chip, the one surface of the first semiconductor chip facing the one surface of the redistribution substrate;
• a plurality of conductive pads that are vertically spaced apart from the plurality of chip pads and are provided on the redistribution substrate;
• and
• a molding body that covers the first semiconductor chip and the one surface of the redistribution substrate,
• wherein the redistribution layer includes:
• a dielectric layer;
• and
• a plurality of redistribution patterns in the dielectric layer,
• wherein each of the plurality of redistribution patterns includes:
• a via body;
• a first pad body that vertically overlaps the via body;
• and
• a line body that extends from the first pad body,
• wherein the via body, the first pad body, and the line body of a same one of the plurality of redistribution patterns are integrally connected to each other,
• wherein a vertical width of the first pad body is greater than a vertical width of the line body of the same one of the plurality of redistribution patterns,
• wherein the semiconductor package further comprises:
• a plurality of connection terminals interposed between and connected to the plurality of chip pads and the plurality of conductive pads;
• a conductive structure that penetrates the molding body;
• and
• an upper redistribution substrate on the molding body and electrically connected to the conductive structure,
• wherein the upper redistribution substrate includes an upper redistribution layer,
• wherein the upper redistribution layer includes:
• an upper dielectric layer;
• and
• a plurality of upper redistribution patterns in the upper dielectric layer,
• wherein each upper redistribution pattern of the plurality of upper redistribution patterns comprises:
• a via body;
• a first pad body that vertically overlaps the via body of the upper redistribution pattern;
• and
• a line body that extends from the first pad body of the upper redistribution pattern, wherein the via body, the first pad body, and the line body of a same one of the plurality of upper redistribution patterns are integrally connected to each other, and
• wherein a vertical width of the first pad body of the upper redistribution pattern is greater than a vertical width of the line body of the upper redistribution pattern.