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US 11,637,057 B2Granted
Uniform via pad structure having covered traces between partially covered pads
AssigneeQUALCOMM Incorporated
InventorsKuiwon Kang, Chin-Kwan Kim, Aniket Patil, Jaehyun Yeon
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Abstract
Examples herein provide more integrated circuit packages that allow direct bonding of semiconductor chips to the package, smaller line/spacing of traces, and uniform vias with no capture or cover pads. For example, an integrated circuit (IC) package may include a plurality of pads and a plurality of traces on a substrate with at least two of the plurality of traces located between two of the plurality of pads, and a dielectric layer that completely covers the plurality of traces and partially covers the plurality of pads.
Claims8
An integrated circuit (IC) package comprising:
- a substrate;
- a plurality of vias that extend from a first side of the substrate to a second side of the substrate opposite the first side of the substrate;
- a plurality of traces proximate to the first side of the substrate, at least one of the plurality of traces located between two of the plurality of vias, and an upper surface of each of the plurality of traces being coplanar with an upper surface of each of the plurality of vias;
- and
- a plurality of pads on the second side of the substrate, wherein the plurality of vias have a uniform shape with no tapers or steps.
2 more elements
Dependencies are inferred from the claim text.