Manufacturing method of chip package structure

A manufacturing method of a chip package structure, comprising:

• disposing a plurality of chips separated from each other on a first insulating layer, wherein each of the chips has an active surface and a back surface opposite to each other, and a peripheral surface connecting the active surface and the back surface, the back surface of each of the chips is in direct contact with the first insulating layer;
• forming a stress buffer layer on the first insulating layer, wherein the stress buffer layer extends and covers the active surface and the peripheral surface of each of the chips, and a bottom surface of the stress buffer layer is aligned with the back surface of each of the chips;
• forming a second insulating layer to cover the stress buffer layer;
• forming a redistribution layer in the second insulating layer, wherein the stress buffer layer has an opening exposing a part of the active surface of each of the chips, and the redistribution layer is electrically connected to each of the chips through the opening;
• forming a plurality of blind holes separated from each other in the second insulating layer, wherein the plurality of blind holes expose a part of the redistribution layer;
• forming a plurality of solder balls respectively in the plurality of blind holes, wherein the plurality of solder balls are electrically connected to the redistribution layer exposed by the plurality of blind holes, and a top surface of each of the solder balls protrudes from an upper surface of the second insulating layer;
• and
• performing a singularizing process, so as to cut off the second insulating layer, the stress buffer layer, and the first insulating layer, thereby forming a plurality of chip package structures separated from each other.