US 11,637,036 B2Granted

Planarization stop region for use with low pattern density interconnects

AssigneeInternational Business Machines Corporation

InventorsCornelius Brown Peethala, Hari Prasad Amanapu, Raghuveer Reddy Patlolla, Koichi Motoyama, Chih-Chao Yang

Life of this patent

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Abstract

Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first dielectric layer from a first dielectric material. A first conductive interconnect is formed having a first conductive interconnect surface. The first conductive interconnect is positioned in a first portion of the first dielectric layer, and the first conductive interconnect surface has a first conductive interconnect surface area. A second conductive interconnect is formed having a second conductive interconnect surface. The second conductive interconnect is above the first conductive interconnect and positioned in a second portion of the first dielectric layer. The second conductive interconnect surface has a second conductive interconnect surface area that is less than a first conductive interconnect surface area of the first conductive interconnect. A planarization stop region is formed above the second conductive interconnect and in a third portion of the first dielectric layer.

Claims10

Dependent claims

A method of forming a multi-layer integrated circuit (IC) structure, the method comprising:

forming a substrate;
forming a dielectric layer comprising a first dielectric material having an overburden comprising a first dielectric layer top surface positioned above the substrate;
forming a top-via conductive interconnect in the dielectric layer, wherein the top-via conductive interconnect comprises a via and a line, wherein the via comprises a via top surface;
forming a planarization stop region within the dielectric layer and over the via top surface, the planarization stop region comprising a planarization stop region surface that is substantially below the first dielectric layer top surface;
and
forming a second dielectric top surface that is substantially co-planar with respect to the planarization stop region surface by applying a planarization process to the overburden using an endpoint detection system;
wherein the planarization stop region comprises a material having characteristics that generate an endpoint detection signal that is sufficiently strong to operate the endpoint detection system independently of an interconnect pattern density (IPD) of the first dielectric layer.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/776,982Filed 30 Jan 2020
Published: US 2021/0242077 A15 Aug 2021
Granted: 25 Apr 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10W 20/063
Of conductive parts of the interconnections: by forming conductive members before forming protective insulating material
H10W 20/087
For dual-damascene structures: involving multiple stacked pre-patterned masks
H10W 20/0633
By forming conductive members before forming protective insulating material: using subtractive patterning of the conductive members
H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs