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US 11,636,915 B2Granted
Command/address channel error detection
AssigneeRambus Inc.
InventorsJohn Eric Linstadt, Frederick A. Ware
Life of this patent
Estimating the term…
Abstract
A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.
Claims20
A controller, comprising:
- a first interface to transmit, to a memory component, an activate command, an access command, and associated address information, the activate command associated with a first bank address value and a row address value, the access command associated with a second bank address value and a column address value;
- a second interface to communicate, with the memory component, data associated with the access command;
- error detection code (EDC) calculation circuitry to calculate a first EDC value based on the first bank address value and the row address value, and to calculate a second EDC value based on the second bank address value and the column address value, and to calculate a third EDC value based on data communicated via the second interface;
- circuitry to associate the second bank address value with stored activate command information, the stored activate command information to be based on the row address;
- code combination circuitry to calculate a fourth EDC value based on the first EDC value, the second EDC value, and the third EDC value;
- a third interface to receive, from the memory component, error detection information;
- and
- circuitry to, based on the error detection information and the fourth EDC value, determine whether an error occurred.
5 more elements
A controller, comprising:
- a first interface to transmit, to a memory component, an activate command, a write command, and associated address information, the activate command associated with a first bank address value and a row address value, the write command associated with a second bank address value and a column address value;
- a second interface to transmit, to the memory component, data associated with the write command;
- error detection code (EDC) calculation circuitry to calculate a first EDC value based on the first bank address value and the row address value, and to calculate a second EDC value based on the second bank address value and the column address value, and to calculate a third EDC value based on the data associated with the write command;
- circuitry to associate the second bank address value with stored activate command information, the stored activate command information to be based on the row address value;
- code combination circuitry to calculate a fourth EDC value based on the first EDC value, the second EDC value, and the third EDC value;
- a third interface to receive, from the memory component, error detection information corresponding to the write command;
- and
- error detection circuitry to, based on the fourth EDC value and the error detection information received from the memory component, determine whether an error has occurred.
5 more elements
A controller, comprising:
- a first interface to transmit, to a memory component, a first command, a second command, and associated address information;
- a second interface to communicate, with the memory component, data associated with the second received command;
- error detection code (EDC) calculation circuitry to calculate a first EDC value based on the first command, and to calculate a second EDC value based on data communicated via the second interface;
- code modulation circuitry to calculate an expected EDC transmit value using an invertible function that is based on the first EDC value and a selected value, the selected EDC value to be provided by a source from a set of sources that include the EDC calculation circuitry providing the second EDC value;
- a third interface to receive, from the memory component, a received EDC value;
- and
- circuitry to, based on the expected EDC value and the received EDC value, determine whether an error occurred.
4 more elements
Dependencies are inferred from the claim text.