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US 11,636,912 B2Granted
ECC buffer reduction in a memory device
AssigneeSamsung Electronics Co., Ltd.
InventorAmit Berman
Life of this patent
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Abstract
A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller includes an error correction code (ECC) circuit. The ECC circuit is configured to determine data rows of first write data that are not all zeros and store the determined data rows in buffer rows of a buffer along with corresponding row indexes. The memory controller is configured to write second data based on the buffer to the memory device.
Claims14
A memory system, comprising:
- a memory device comprising a plurality of memory cells;
- and
- a memory controller comprising an error correction code (ECC) circuit,
- wherein the ECC circuit is configured to determine data rows of first write data that are not all zeros and store the determined data rows in buffer rows of a buffer along with corresponding row indexes, and
- wherein the memory controller is configured to write second data based on the buffer to the memory device.
2 more elements
A computer-implemented method for programming data to a memory system, the method comprising:
- receiving, by a memory controller, a write request including first write data;
- determining, by an error correction code (ECC) circuit, data rows of the first write data that are not all zero;
- generating, by the ECC circuit, compressed data including the determined data rows and corresponding row indexes within the first write data;
- and
- writing, by the memory controller, second write data based on the compressed data to the memory device.
2 more elements
Dependencies are inferred from the claim text.