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US 11,636,910 B2Granted
Apparatus configured to perform a test operation
AssigneeSK hynix Inc.
InventorsHyeong Soo Jeong, Dong Beom Lee
Life of this patent
Estimating the term…
Abstract
An apparatus includes a selection data generation circuit configured to generate selection data from fuse data or generate the selection data having a preset test input pattern, depending on whether a failure test is entered; and a failure flag generation circuit configured to generate latch data by latching the selection data, and generate a failure flag by detecting whether the latch data has a preset test pattern.
Claims13
An apparatus comprising:
- a selection data generation circuit configured to generate selection data from fuse data or pattern data having a preset test input pattern, depending on whether a failure test is entered, wherein the pattern data is output from the selection data generation circuit having the preset test input pattern where at least two bits of the pattern have different values;
- and
- a failure flag generation circuit configured to generate latch data by latching the selection data, and generate a failure flag by detecting whether the latch data has a preset test pattern, wherein the failure flag generation circuit comprises:
- a first internal failure flag generation circuit configured to generate first latch data by latching first selection data, and generate a first internal failure flag by detecting whether the first latch data has the preset test pattern;
- a second internal failure flag generation circuit configured to generate second latch data by latching second selection data, and generate a second internal failure flag by detecting whether the second latch data has the preset test pattern;
- and
- a failure flag output circuit configured to output one of the first and second internal failure flags as the failure flag based on first and second test control signals.
4 more elements
An apparatus comprising:
- a selection data generation circuit configured to generate selection data from fuse data or pattern data having one of first and second test input patterns, depending on whether a failure test is entered, wherein the pattern data is output from the selection data generation circuit having a preset test input pattern where at least two bits of the pattern have different values;
- an
- a failure flag generation circuit configured to generate latch data by latching the selection data, and generate a failure flag by detecting whether the latch data has a preset test pattern, wherein the failure flag generation circuit comprises:
- a first internal failure flag generation circuit configured to generate first latch data by latching first selection data, and generate a first internal failure flag by detecting whether the first latch data has the preset test pattern;
- a second internal failure flag generation circuit configured to generate second latch data by latching second selection data, and generate a second internal failure flag by detecting whether the second latch data has the preset test pattern;
- and
- a failure flag output circuit configured to output one of the first and second internal failure flags as the failure flag based on first and second test control signals.
4 more elements
Dependencies are inferred from the claim text.