Global-local read calibration

A method, comprising:

• applying, by a calibration circuit of a memory device and to a plurality of memory cells in the memory device, first test voltages at a first interval over a first voltage range;
• determining, by the memory device for the first test voltages respectively, first counts of memory cells, among the plurality of memory cells, having a predetermined state when the first test voltages are applied;
• identifying, based on the first counts for the first test voltages respectively, a second voltage range within the first voltage range;
• applying, by the calibration circuit and to the plurality of memory cells, second test voltages within the second voltage range at a second interval smaller than the first interval;
• and
• determining, by the memory device for the second test voltages respectively, second counts of memory cells, among the plurality of memory cells, having the predetermined state when the second test voltages are applied.

A memory sub-system, comprising:

• a processing device;
• and
• at least one memory device having a plurality of memory cells formed on an integrated circuit die;
• wherein the processing device is configured to transmit, to the memory device, a command configured to identify the plurality of memory cells;
• and
• wherein in response to the command, the memory device is configured to:
• apply, to the plurality of memory cells in the memory device, first test voltages at a first interval over a first voltage range;
• determine, for the first test voltages respectively, first counts of memory cells, among the plurality of memory cells, having a predetermined state when the first test voltages are applied;
• identify, based on the first counts for the first test voltages respectively, a second voltage range within the first voltage range;
• apply, to the plurality of memory cells, second test voltages within the second voltage range at a second interval smaller than the first interval;
• and
• determine, by the memory device for the second test voltages respectively, second counts of memory cells, among the plurality of memory cells, having the predetermined state when the second test voltages are applied.