Temperature compensation for unselected sub-block inhibit bias for mitigating erase disturb

A controller in communication with a memory apparatus including a block including memory cells connected to word lines and arranged in strings, the block being divided into a first sub-block and a second sub-block each configured to be erased as a whole in an erase operation, the controller being in communication with a temperature measuring circuit configured to detect an ambient temperature of the memory apparatus, the word lines of the memory apparatus overlay one another in a stact and each of the strings comprises a memory hole extending vertically through the stack and having a plurality of tiers including a lower tier and an upper tier vertically aligned with one another in the stack and the lower tier comprises the first sub-block of the memory cells and the upper tier comprises the second sub-block of the memory cells, the erase operation being selected from the group consisting of a two-sided erase operation, a source side erase operation, and a drain side erase operation and each of the strings is coupled to a bit line on a drain side of each the strings and a source line on a source side of each the strings, the controller configured to:

• determine a word line inhibit voltage based on the ambient temperature;
• instruct the memory apparatus to apply an erase voltage to each of the strings while simultaneously applying a word line erase voltage to the word lines associated with a selected one of the first and second sub-blocks to encourage erasing of the memory cells and the word line inhibit voltage to the word lines associated with an unselected one of the first and second sub-blocks to discourage erasing of the memory cells in the erase operation;
• instruct the memory apparatus to apply the erase voltage to the bit line of each of the strings associated with the selected one of the first sub-block and the second sub-block during the drain side erase operation;
• instruct the memory apparatus to apply the erase voltage to the source line of each of the strings associated with the selected one of the first sub-block and the second sub-block during the source side erase operation;
• and
• instruct the memory apparatus to apply the erase voltage to both the bit line and the source line of each of the strings associated with the selected one of the first sub-block and the second sub-block during the two-sided erase operation.

A method of operating a memory apparatus including a block including memory cells connected to word lines and arranged in strings, the block being divided into a first sub-block and a second sub-block each configured to be erased as a whole in an erase operation, the memory apparatus including a temperature measuring circuit configured to detect an ambient temperature of the memory apparatus, the word lines of the memory apparatus overlay one another in a stack and each of the strings comprises a memory hole extending vertically through the stack and having a plurality of tiers including a lower tier and an upper tier vertically aligned with one another in the stack and the lower tier comprises the first sub-block of the memory cells and the upper tier comprises the second sub-block of the memory cells, and the erase operation is selected from the group consisting of a two-sided erase operation, a source side erase operation, and a drain side erase operation and each of the strings is coupled to a bit line on a drain side of each the strings and a source line on a source side of each the strings, the method comprising the steps of:

• determining a word line inhibit voltage based on the ambient temperature;
• applying an erase voltage to each of the strings while simultaneously applying a word line erase voltage to the word lines associated with a selected one of the first and second sub-blocks to encourage erasing of the memory cells and the word line inhibit voltage to the word lines associated with an unselected one of the first and second sub-blocks to discourage erasing of the memory cells in the erase operation;
• applying the erase voltage to the bit line of each of the strings associated with the selected one of the first sub-block and the second sub-block during the drain side erase operation;
• applying the erase voltage to the source line of each of the strings associated with the selected one of the first sub-block and the second sub-block during the source side erase operation;
• and
• applying the erase voltage to both the bit line and the source line of each of the strings associated with the selected one of the first sub-block and the second sub-block during the two-sided erase operation.