Memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsBilal Ahmad Janjua, Sung Whan Seo
Life of this patent
Estimating the term…
Abstract
A memory device includes a charge pump connected to a power supply voltage and including a plurality of stages to output an output voltage, a stage counter configured to output a count value that incrementally increases to a number of the stages, and a regulator configured to compare the output voltage with a reference output voltage of the charge pump that is generated using the incrementally increasing count value obtained by the stage counter, and to output a pump operation signal at a time when the reference output voltage becomes greater than or equal to the output voltage, wherein the charge pump operates in response to the pump operation signal.
Claims20
A memory device comprising:
- a memory cell region including a first metal pad;
- a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;
- a charge pump comprising a plurality of stages to output an output voltage in the peripheral circuit region;
- a stage counter in the peripheral circuit region configured to output a count value that incrementally increases to a number of the plurality of stages;
- and
- a regulator in the peripheral circuit region configured to output a pump operation signal by comparing the output voltage with a reference output voltage of the charge pump, the reference output voltage being generated using the incrementally increasing count value obtained by the stage counter,
- wherein the charge pump is configured to operate in response to the pump operation signal.
A memory device comprising:
- a memory cell region including a first metal pad;
- a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;
- a charge pump comprising a plurality of stages in the peripheral circuit region;
- a stage counter in the peripheral circuit region configured to output a respective stage reference signal corresponding to each stage from among the plurality of stages;
- and
- a regulator in the peripheral circuit region configured to generate a stage operation signal different from the stage reference signal based on the stage reference signal and a first stage control signal,
- wherein the charge pump is configured to generate an output voltage using a number of stages corresponding to the stage reference signal or the stage operation signal output by the regulator.
A memory device comprising:
- a memory cell region including a first metal pad;
- a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;
- a memory cell array in the memory cell region comprising a plurality of memory cells;
- and
- a voltage generator in the peripheral circuit region configured to generate a program voltage of a memory cell in the memory cell array,
- wherein the voltage generator comprises:
- a charge pump configured to generate the program voltage, and
- a regulator configured to generate a pump operation signal by comparing a reference output voltage of the charge pump, generated using at least one of a plurality of stages, with an output voltage of the charge pump as it recovers from the program voltage to a ground voltage after the charge pump generates the program voltage, and
- wherein the charge pump is configured to operate in response to the pump operation signal.
Dependencies are inferred from the claim text.