Semiconductor memory device and method of operating the same

A semiconductor memory device, comprising:

• a memory block including a plurality of memory cells;
• and
• a control logic configured to control a peripheral circuit to perform a plurality of read operations on selected memory cells among the plurality of memory cells,
• wherein each of the plurality of read operations includes a bit line precharge operation increasing a voltage of a plurality of bit lines to a predetermined precharge voltage, an evaluation operation, and a sensing operation, wherein
• the control logic is configured to control the peripheral circuit to float a common source line coupled to the memory block during at least a partial period of a period in which the voltage of the plurality of bit lines increases, and
• wherein the period includes the sensing operation of a first read operation and the bit line precharge operation of a second read operation following the first read operation.

A method of operating a semiconductor memory device, the method comprising:

• performing a read operation on selected memory cells among a plurality of memory cells, the read operation including:
• precharging a voltage of bit lines coupled to a memory block including the selected memory cells;
• applying a read voltage to a selected word line coupled to the selected memory cells among word lines coupled to the memory block, and applying a read pass voltage to an unselected word line other than the selected word line among the word lines;
• and
• temporarily storing information indicating whether the selected memory cells are turned on, based on the voltage of each of the bit lines, wherein precharging the voltage of the bit lines coupled to the memory block including the selected memory cells comprises floating a common source line coupled to the memory block during at least a partial period of a period in which the voltage of the bit lines increases.

A semiconductor memory device, comprising:

• a memory block including a plurality of memory cells;
• a peripheral circuit configured to perform a program operation on selected memory cells among the plurality of memory cells;
• and
• a control logic configured to control the program operation of the peripheral circuit, wherein
• the program operation includes a plurality of program loops, each of the plurality of program loops includes a program phase and a verify phase,
• the verify phase includes a bit line precharge operation, an evaluation operation, and a sensing operation, and
• the control logic is configured to control the peripheral circuit to float a common source line coupled to the memory block during at least a partial period of a period of the bit line precharge operation, in which a voltage of a plurality of bit lines coupled to the memory block increases.

An apparatus, comprising:

• a storage area configured to store instructions;
• and
• at least one processor configured to execute the instructions to control a read operation including a bit line precharge operation increasing a voltage of a plurality of bit lines to a predetermined precharge voltage, an evaluation operation, and a sensing operation, wherein the at least one processor is configured to control the read operation to:
• float a common source line coupled to a memory block during at least a partial period of a period in which the voltage of the plurality of bit lines increases.