Peak current and program time optimization through loop dependent voltage ramp target and timing control
AssigneeSanDisk Technologies LLC
InventorsYanjie Wang, Henry Chin, Guirong Liang, Jianzhi Wu
Life of this patent
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AssigneeSanDisk Technologies LLC
InventorsYanjie Wang, Henry Chin, Guirong Liang, Jianzhi Wu
Estimating the term…
An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a predicted parasitic capacitance associated with the programming state of the control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.
A non-volatile memory device, comprising:
A method of controlling a non-volatile memory device that includes a plurality of memory cells respectively electrically coupled to a plurality of bit lines and includes control circuitry coupled to the plurality of memory cells and configured to program the memory cells in a programming operation that includes a plurality of program loops, the method comprising the steps of:
An apparatus, comprising:
Dependencies are inferred from the claim text.