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US 11,636,896 B2Granted
Memory cell array circuit and method of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChin-I Su, Chung-Cheng Chou, Yu-Der Chih, Zheng-Jun Lin
Life of this patent
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Abstract
A memory circuit includes a first driver circuit, a first column of memory cells coupled to the first driver circuit, a first current source, a tracking circuit configured to track a leakage current of the first column of memory cells, and a footer circuit coupled to the first column of memory cells, the first current source and the tracking circuit.
Claims20
A memory circuit comprising:
- a first driver circuit, wherein the first driver circuit comprises:
- a first amplifier comprising a first input terminal, a second input terminal and a first output terminal;
- and
- a first transistor comprising a first gate and a first drain, wherein the first gate is coupled to the first output terminal, and the first drain is coupled to the second input terminal;
- a first column of memory cells coupled to the first driver circuit;
- a first current source;
- a tracking circuit configured to track a leakage current of the first column of memory cells, wherein the tracking circuit comprises:
- a second driver circuit, and the second driver circuit comprises:
- a second amplifier comprising a third input terminal, a fourth input terminal and a second output terminal;
- and
- a second transistor comprising a second gate and a second drain, wherein the second gate is coupled to the second output terminal, and the second drain is coupled to the fourth input terminal;
- and
- a footer circuit coupled to the first column of memory cells, the first current source and the tracking circuit.
10 more elements
A memory circuit comprising:
- a first driver circuit, wherein the first driver circuit comprises:
- a first amplifier comprising a first input terminal, a second input terminal and a first output terminal;
- and
- a first transistor comprising a first gate and a first drain, wherein the first gate is coupled to the first output terminal, and the first drain is coupled to the second input terminal;
- a memory cell array including a first column of memory cells coupled to the first driver circuit;
- a second driver circuit;
- a first column of tracking cells configured to track a leakage current of the first column of memory cells, and coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit;
- and
- a header circuit coupled to the first driver circuit and the second driver circuit.
6 more elements
A memory circuit comprising:
- a first driver circuit, wherein the first driver circuit comprises:
- a first amplifier comprising a first input terminal of the first amplifier, a second input terminal of the first amplifier and a first output terminal of the first amplifier;
- and
- a first transistor comprising a first gate and a first drain, wherein the first gate is coupled to the first output terminal of the first amplifier, and the first drain is coupled to the second input terminal of the first amplifier;
- a first column of memory cells coupled to the first driver circuit;
- a second driver circuit;
- a first column of tracking cells coupled to the second driver circuit, and configured to track a leakage current of the first column of memory cells, and coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit;
- and
- a header circuit coupled between the first driver circuit and the second driver circuit.
6 more elements
Dependencies are inferred from the claim text.