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US 11,636,895 B2Granted
Non-volatile resistive memory device including a plurality of write modes
AssigneeSamsung Electronics Co., Ltd.
InventorsCheaouk Lim, Jung Sunwoo, Kwangjin Lee
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Abstract
A writing method for a non-volatile memory device includes; performing a sensing operation, comparing write data with read data retrieved by the sensing operation, determining whether the write data is set state when the write data and the read data are the same, performing a set operation when the write data is set state, and not performing a write operation when the write data is not set data.
Claims20
A non-volatile memory (NVM) device comprising:
- a memory cell array including a plurality of resistive memory cells connected to a plurality of bit lines and a plurality of word lines;
- a word line driver configured to select one of the plurality of word lines in response to an address and apply a word line voltage to the selected word line;
- a bit line driver configured to select one of the plurality of bit lines in response to the address and apply a bit line voltage to the selected bit line;
- a write circuit configured to generate the bit line voltage and the word line voltage in response to a write control signal;
- a read circuit configured to read data from a resistive memory cell connected to the selected word line and the selected bit line in response to a read control signal;
- an input and output (I/O) circuit configured to receive write data from an external device;
- and
- control logic configured to:
- select a write mode from a plurality of write modes,
- generate the write control signal based on at least one of the selected write mode, the write data, and the read data, and
- generate the read control signal based on at least one of the selected write mode and the write data, wherein:
- at least one of the plurality of write modes defines a write operation that performs a read operation,
- the bit line voltage having a second read level is applied to the selected bit line when the read operation is performed, and
- the second read level is higher than a first read level for another read operation performed in a read mode that is not associated with any of the plurality of write modes.
11 more elements
A non-volatile memory (NVM) device comprising:
- a memory cell array including:
- a plurality of resistive memory cells connected to a plurality of bit lines and a plurality of word lines, and
- a plurality of memory cell layers vertically stacked in a direction perpendicular to a substrate;
- a word line driver that selects one of the plurality of word lines as a selected word line in response to an address and applies a word line voltage to the selected word line;
- a bit line driver that selects one of the plurality of bit lines as a selected bit line in response to the address and applies a bit line voltage to the selected bit line;
- a write circuit that generates the bit line voltage and the word line voltage in response to a write control signal;
- a read circuit that reads read data from a resistive memory cell connected to the selected word line and the selected bit line in response to a read control signal;
- an input and output (I/O) circuit that receives write data from an external device;
- and
- control logic that:
- selects a selected write mode from a plurality of write modes according to a distance of a memory cell layer, among the plurality of memory cell layers, from the substrate,
- generates the write control signal based on the selected write mode, the write data, or the read data, and
- generates the read control signal based on the selected write mode or the write data.
10 more elements
A non-volatile memory (NVM) device comprising:
- a memory cell array including a plurality of resistive memory cells connected to a plurality of bit lines and a plurality of word lines;
- a word line driver that selects one of the plurality of word lines as a selected word line in response to an address and applies a word line voltage to the selected word line;
- a bit line driver that selects one of the plurality of bit lines as a selected bit line in response to the address and applies a bit line voltage to the selected bit line;
- a write circuit that generates the bit line voltage and the word line voltage in response to a write control signal;
- a read circuit that reads read data from a resistive memory cell connected to the selected word line and the selected bit line in response to a read control signal;
- an input and output (I/O) circuit that receives write data from an external device;
- and
- control logic that:
- selects a read skip aggressive data comparison write (RDSKIP aDCW) mode that does not perform:
- a write operation when both the write data and the read data are reset data;
- and
- a sensing operation when the write data is set data, and generates the write control signal based on the RDSKIP aDCW mode, the write data, or the read data.
9 more elements
Dependencies are inferred from the claim text.