Memory system and operation method thereof

A memory system, comprising a plurality of memory chips connected to each other, each of the memory chips comprising:

• a memory array storing a data;
• a read/write data strobe pin connected to read/write data strobe pins of other memory chips;
• a look-up table storage device storing a plurality of trimming shift values related to a number of chip connections in advance;
• a chip number identification circuit coupled to the look-up table storage device and configured to identify a current number of chip connections according to a state information, and find a selected trimming shift value from the look-up table storage device accordingly;
• and
• a control logic circuit coupled to the memory array, the read/write data strobe pin, the look-up table storage device, and the chip number identification circuit, and configured to transmit a data signal in response to a clock signal and adjust a setup and hold time between the clock signal and the data signal according to the selected trimming shift value.