Memory device for supporting new command input scheme and method of operating the same

A memory controller comprising:

• a clock pin configured to transmit a clock signal to a memory device;
• row pins configured to transmit a first active command for one memory bank of the memory device and a first precharge command for the one memory bank during a first time period, and transmit a second active command for the one memory bank and a second precharge command for the one memory bank during a second time period, and
• column pins configured to transmit a first read command or a first write command for the one memory bank during the first time period, and transmit a second read command or a second write command for the one memory bank during the second time period,
• wherein during the first time period, the memory controller is configured to transmit the first active command to the memory device during one and a half (1.5) cycles of the clock signal, transmit the first read command or the first write command to the memory device during one (1) cycle of the clock signal after transmitting the first active command, and transmit the first precharge command to the memory device during a half (0.5) cycle of the clock signal after transmitting the first read command or the first write command, and
• wherein during the second time period, the memory controller is configured to transmit the second active command to the memory device during the 1.5 cycles of the clock signal, transmit the second read command or the second write command to the memory device during the 1 cycle of the clock signal after transmitting the second active command, and transmit the second precharge command to the memory device during the 0.5 cycle of the clock signal after transmitting the second read command or the second write command.

A memory system comprising:

• a package substrate;
• an interposer stacked on the package substrate;
• a memory device stacked on the interposer, the memory device including a clock pin, row pins and column pins;
• and
• a memory controller stacked on the interposer, the memory controller configured to transmit a first row command for one memory bank of the memory device to the memory device during a first time period, transmit a second row command for the one memory bank to the memory device during a second time period, and transmit a clock signal to the memory device,
• wherein the interposer is configured to connect the memory device and the memory controller,
• wherein the memory device is configured to decode the first row command received through the row pins during the first time period, and decode the second row command received through the row pins during the second time period,
• wherein the first row command is transmitted during a half (0.5) cycle of the clock signal corresponding to a rising edge of the clock signal,
• wherein the second row command is transmitted during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal, and
• wherein the first row command corresponds to a first precharge command and the second row command corresponds to a second precharge command.