Gate driving circuit and display device including the same

A display device comprising:

• a display panel comprising a plurality of pixels respectively connected to a plurality of data lines and respectively connected to a plurality of gate lines;
• a data driving circuit configured to drive the plurality of data lines;
• a gate driving circuit configured to drive the plurality of gate lines;
• a timing controller configured to receive an image signal and a control signal, control the data driving circuit and the gate driving circuit to display an image on the display panel, and output a gate pulse signal;
• and
• a voltage generating circuit configured to output a first clock signal and a first voltage in response to the gate pulse signal,
• wherein the voltage generating circuit is configured to change the first voltage such that the first voltage sequentially has a first level and a second level different from the first level during an initialization mode, and
• the gate driving circuit comprises a plurality of driving stages, each of the plurality of driving stages configured to provide a gate signal to a corresponding gate line among the plurality of gate lines,
• wherein each of the plurality of driving stages is configured to discharge the corresponding gate line in response to the first voltage and the first clock signal during the initialization mode,
• wherein each of the plurality of driving stages comprises:
• a first transistor connected between a first clock terminal for receiving the first clock signal and a gate output terminal, the first transistor comprising a gate electrode connected to a first node;
• a second transistor configured to transmit a first carry signal to the first node;
• and
• a third transistor connected between the first node and a first voltage terminal for receiving the first voltage, the third transistor comprising a gate electrode connected to the first voltage terminal,
• wherein each of the plurality of driving stages further comprises a fourth transistor connected between the gate output terminal and a second voltage terminal for receiving a second voltage different from the first voltage, the fourth transistor comprising a gate electrode connected to a second clock terminal for receiving a second clock signal different from the first clock signal,
• wherein when the first voltage is changed to have the second level, the third transistor and the first transistor are turned on, respectively.