Method for controlling timing controller chip of display panel, and display panel

A method for controlling a timing controller chip of a display panel, comprising steps of:

• generating a write protection level and outputting the same to a write protection pin of a memory chip by a pulse modulator;
• detecting an actual level value of the write protection pin by a detection circuit;
• comparing the actual level value with the write protection level, and sending a comparison result to the timing controller chip by the detection circuit;
• outputting a corresponding enable signal to the timing controller chip according to the comparison result by the detection circuit;
• if the comparison result is that the actual level value is not equal to the write protection level, sending a first enable signal to the timing controller chip by the detection circuit:
• controlling to disconnect an inter-integrated circuit bus arranged between the timing controller chip and the memory chip according to the first enable signal by the timing controller chip;
• skipping outputting an inter-integrated circuit signal to the memory chip by the timing controller chip;
• restarting a circuit;
• re-detecting the actual level value of the write protection pin by the detection circuit;
• if the comparison result is that the actual level value is equal to the write protection level, sending a second enable signal to the timing controller chip by the detection circuit;
• controlling to enable the inter-integrated circuit bus arranged between the timing controller chip and the memory chip according to the second enable signal by the timing controller chip;
• outputting an inter-integrated circuit signal to the memory chip, and reading an initialization configuration code stored in the memory chip by the timing controller chip;
• and
• performing initialization configuration according to the read initialization configuration code by the timing controller chip.

A display panel, comprising:

• a memory chip, comprising a write protection pin, and storing an initialization code of a timing controller chip;
• the timing controller chip, reading the initialization code of the timing controller chip and performing initialization configuration;
• an inter-integrated circuit bus, arranged between the memory chip and the timing controller chip;
• a pulse modulator, outputting a write protection level to the write protection level-pin;
• and
• a detection circuit, arranged in the pulse modulator, and configured to detect an actual level value of the write protection pin, compare the actual level value with the write protection level, and control to disconnect or enable the inter-integrated circuit bus arranged between the memory chip and the timing controller chip according to a comparison result.