Machine learning-based algorithm to accurately predict detail-route DRVS for efficient design closure at advanced technology nodes

A system comprising:

• a memory storing instructions;
• and
• a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
• receive a first list of features associated with a placed netlist of a first circuit design comprising a plurality of library cells;
• receive a second list of features from a global router performing a global route of the first circuit design;
• receive a label associated with each of the plurality of library cells in the first circuit design from a detailed router performing a detailed route of the design;
• predict a number of design rules violations of the first circuit design in accordance with the received first and second lists and the labels;
• and
• upsample a subset of the labels.

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

• perform placement of a netlist associated with a first circuit design;
• receive a first list of features associated with the placed netlist;
• perform a global route of the first circuit design;
• receive a second list of features;
• perform a detailed route of the first circuit design by a detailed router;
• receive a label associated with each of a plurality of library cells in the first circuit design;
• predict a number of design rules violations of the first circuit design in accordance with the received first and second lists and the labels;
• select features, from one or more of the first list and the second list, whose degree of correlations with the design rules violations is greater than a first value.