Long-short term memory (LSTM) cells on spiking neuromorphic hardware
AssigneeInternational Business Machines Corporation
InventorsRathinakumar Appuswamy, Michael Beyeler, Pallab Datta, Myron Flickner, Dharmendra S. Modha
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Abstract
Long-short term memory (LSTM) cells on spiking neuromorphic hardware are provided. In various embodiments, such systems comprise a spiking neurosynaptic core. The neurosynaptic core comprises a memory cell, an input gate operatively coupled to the memory cell and adapted to selectively admit an input to the memory cell, and an output gate operatively coupled to the memory cell an adapted to selectively release an output from the memory cell. The memory cell is adapted to maintain a value in the absence of input.
Claims19
A system comprising:
- a spiking neurosynaptic core comprising
- a memory cell,
- an input gate operatively coupled to the memory cell and adapted to selectively admit an input to the memory cell during a first time interval, wherein
- the input gate has a membrane potential,
- the input gate is operatively coupled to a plurality of spiking neurons, the input gate is configured to update its membrane potential according to a number of spikes received from the plurality of spiking neurons during a second time interval preceding the first time interval,
- the input gate is configured to block the input to the memory cell when the membrane potential exceeds a predetermined threshold, wherein the blocking of the input comprises preventing all input signals to the memory cell, and wherein the membrane potential controls the input gate, and
- an output gate operatively coupled to the memory cell and adapted to selectively release an output from the memory cell, and wherein
- the memory cell is adapted to maintain a value in the absence of input.
A method comprising:
- configuring a neuromorphic system with a predetermined plurality of configuration parameters comprising synaptic weights and neuronal biases, the neuromorphic system comprising
- a memory cell,
- an input gate operatively coupled to the memory cell and adapted to selectively admit an input to the memory cell during a first time interval, wherein
- the input gate has a membrane potential,
- the input gate is operatively coupled to a plurality of spiking neurons, the input gate is configured to update its membrane potential according to a number of spikes received from the plurality of spiking neurons during a second time interval preceding the first time interval,
- the input gate is configured to block the input to the memory cell when the membrane potential exceeds a predetermined threshold, wherein the blocking of the input comprises preventing all input signals to the memory cell, and wherein the membrane potential controls the input gate, and
- an output gate operatively coupled to the memory cell and adapted to selectively release an output from the memory cell, and wherein
- the memory cell is adapted to maintain a value in the absence of input;
- receiving a first sequence of spikes at the neuromorphic system;
- transcoding the first sequence of spikes by the neuromorphic system via the memory cell into a second sequence of spikes the transcoding being determined by the synaptic weights and neuronal biases.
A computer program product for providing a long-short term memory, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable by a processor to cause the processor to perform a method comprising:
- configuring a neuromorphic system with a predetermined plurality of configuration parameters comprising synaptic weights and neuronal biases, the neuromorphic system comprising
- a memory cell,
- an input gate operatively coupled to the memory cell and adapted to selectively admit an input to the memory cell during a first time interval, wherein
- the input gate has a membrane potential,
- the input gate is operatively coupled to a plurality of spiking neurons, the input gate is configured to update its membrane potential according to a number of spikes received from the plurality of spiking neurons during a second time interval preceding the first time interval,
- the input gate is configured to block the input to the memory cell when the membrane potential exceeds a predetermined threshold, wherein the blocking of the input comprises preventing all input signals to the memory cell, and wherein the membrane potential controls the input gate, and
- an output gate operatively coupled to the memory cell and adapted to selectively release an output from the memory cell, and wherein
- the memory cell is adapted to maintain a value in the absence of input;
- receiving a first sequence of spikes at the neuromorphic system;
- transcoding the first sequence of spikes by the neuromorphic system via the memory cell into a second sequence of spikes the transcoding being determined by the synaptic weights and neuronal biases.
Dependencies are inferred from the claim text.