Synapse circuit and arithmetic device

A synapse circuit modeling a synapse incorporating spike timing dependent synaptic plasticity (STDP) and transmitting a signal, the synapse circuit comprising:

• a buffer that changes, in a case that an output signal to be output to a subsequent-stage circuit that models a neuron in a subsequent stage of the synapse has a first logical value in a first mode, the output signal to a second logical value at a timing when an input signal, received from a preceding stage circuit that models a neuron in a preceding stage of the synapse, exceeds a first threshold level and that changes, in a case that the output signal has the first logical value in a second mode, the output signal to the second logical value at a timing when the input signal exceeds a reference level lower than the first threshold level;
• an adjusting unit that stores a coefficient indicative of a signal transmission speed in the synapse and adjusts the first threshold level depending on the coefficient;
• and
• a mode switching unit that acquires a spike signal indicating that a spike is generated, and that operates the buffer in the first mode during a period in which the spike is not generated, and operates the buffer in the second mode during a period in which the spike is generated, wherein
• the buffer includes a Schmitt trigger circuit, the Schmitt trigger circuit comprising:
• an input terminal to which the input signal is applied;
• an output terminal that outputs the output signal,
• a positive side power supply terminal to which a positive side power supply voltage is applied;
• and
• a negative side power supply terminal to which a negative side power supply voltage is applied,
• a first field effect transistor that is turned on when a gate-source voltage is equal to or higher than a threshold voltage, the first field effect transistor having a gate connected to the input terminal and a source connected to the negative side power supply terminal,
• a second field effect transistor that is turned on when a gate-source voltage is equal to or higher than a threshold voltage, the second field effect transistor having a gate connected to the input terminal, a source connected to a drain of the first field effect transistor, and a drain connected to the output terminal;
• a third field effect transistor that is turned on when a gate-source voltage is equal to or higher than a threshold voltage, the third field effect transistor having a gate connected to the output terminal and a source connected to the source of the second field effect transistor;
• a fourth field effect transistor that is turned on when a gate-source voltage is equal to or lower than a threshold voltage, the fourth field effect transistor having a gate connected to the input terminal and a source connected to the positive side power supply terminal;
• a fifth field effect transistor that is turned on when a gate-source voltage is equal to or lower than a threshold voltage, the fifth field effect transistor having a gate connected to the input terminal, a source connected to a drain of the fourth field effect transistor, and a drain connected to the output terminal;
• and
• a sixth field effect transistor that is turned on when a gate-source voltage is equal to or lower than a threshold voltage, the sixth field effect transistor having a gate connected to the output terminal and a source connected to the source of the fifth field effect transistor,
• the adjusting unit is a variable resistor set to a resistance value depending on the coefficient, and is connected between the negative side power supply terminal and a generation source of the negative side power supply voltage, and
• the spike signal is applied to a drain of the third field effect transistor and a drain of the sixth field effect transistor.