Integrated circuit and layout method for standard cell structures

A method, comprising:

• scanning a circuit layout design to identify a plurality of vertical cell regions, wherein each vertical cell region comprises a plurality of standard cells arranged in a vertical direction, and wherein each standard cell has a height extending in the vertical direction and a width extending in a horizontal direction;
• scanning the circuit layout design to identify a first pin connector of a first standard cell of a first vertical cell region, wherein the first pin connector is electrically coupled to an active region extending in the horizontal direction;
• scanning the circuit layout design to identify a second pin connector of a second standard cell of a second vertical cell region, wherein the first and second vertical cell regions are adjacent to each other, and wherein the second pin connector is electrically coupled to the active region;
• determining a distance between the first and second pin connectors;
• and
• reducing the distance between the first and second pin connectors, wherein reducing the distance comprises performing an action on at least one of the first and second standard cells.

A method, comprising:

• scanning a vertical cell region of a circuit layout design to determine a first plurality of standard cells having a two-fin structure layout and a second plurality of standard cells having a one-fin structure layout, wherein the first and second pluralities of standard cells are arranged in a vertical direction;
• identifying a first pin connector of a first standard cell from the first plurality of standard cells;
• identifying a second pin connector of a second standard cell from the second plurality of standard cells, wherein a distance between the first and second pin connectors extends in the vertical direction;
• and
• moving the first or second standard cell along the vertical direction to reduce the distance.