Metal cut region location system

An integrated circuit (IC) layout diagram generation system comprising:

• a processor;
• and
• a non-transitory, computer readable storage medium including computer program code for one or more programs, the non-transitory, computer readable storage medium and the computer program code being configured to, with the processor, cause the system to:
• receive a cell from a cell library, the cell being free from including a first metal layer cut region;
• align a border segment of the cell at a predetermined location between adjacent second metal layer tracks;
• position the cell relative to a first metal layer cut region alignment pattern based on the second metal layer tracks;
• overlap the cell with a first metal layer cut region based on the first metal layer cut region alignment pattern;
• and
• generate an IC layout diagram of an IC device based on the cell and the first metal layer cut region.

An integrated circuit (IC) layout diagram generation system comprising:

• a processor;
• and
• a non-transitory, computer readable storage medium including computer program code for one or more programs, the non-transitory, computer readable storage medium and the computer program code being configured to, with the processor, cause the system to:
• receive first and second cells from a cell library;
• align a first border segment of the first cell with a first track of a plurality of tracks corresponding to a second metal layer;
• align a second border segment of the first cell and a first border segment of the second cell with a second track of the plurality of tracks;
• align a second border segment of the second cell with a third track of the plurality of tracks;
• position the first and second cells relative to a first metal layer cut region alignment pattern based on the plurality of tracks;
• overlap at least one of the first or second cells with a first metal layer cut region based on the first metal layer cut region alignment pattern;
• and
• generate an IC layout diagram of an IC device based on the first and second cells and the first metal layer cut region.