Performance tuning of a hardware description language simulator

A system comprising:

• a memory storing instructions;
• and
• a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
• generate a plurality of recommendations corresponding to a first subsystem of a hardware description language (HDL) simulation system using one or more optimization applications;
• generate a first aggregate recommendation by combining the plurality of recommendations corresponding to the first subsystem of the HDL simulation system;
• and
• update a configuration of the first subsystem of the HDL simulation system based on the first aggregate recommendation, wherein the HDL simulation system is configured to simulate a circuit design using the updated configuration during execution of the first subsystem.

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

• generate a plurality of recommendations corresponding to a first subsystem of a hardware description language (HDL) simulation system, wherein the plurality of recommendations are generated using one or more optimization applications;
• generate a first aggregate recommendation by combining the plurality of recommendations corresponding to the first subsystem of the HDL simulation system;
• and
• update a configuration of the first subsystem of the HDL simulation system based on the first aggregate recommendation, wherein the HDL simulation system is configured to simulate a circuit design using the updated configuration during execution of the first subsystem.