Artificial reality system with multi-stage boot process
AssigneeMeta Platforms Technologies, LLC
InventorsShrirang Madhav Yardi, Neeraj Upasani, Dinesh Patil
Life of this patent
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Abstract
Techniques are described for improving security of a boot sequence of a system, such as an artificial reality system. In some examples, a method includes configuring, by a boot sequencing system, attack detection circuitry based on configuration information accessed from a first storage device; after configuring the attack detection circuitry, starting, by the boot sequencing system, a root of trust processor to initiate a boot sequence; enabling access, by the root of trust processor during the boot sequence, to secret information stored in a second storage device.
Claims18
A method comprising:
- receiving, by a boot sequencing system and on a port, a voltage;
- responsive to receiving the voltage on the port, generating, by the boot sequencing system, an internal reset signal and a first internal clock signal from a first clock source;
- configuring, by the boot sequencing system, attack detection circuitry based on configuration information accessed from a first storage device;
- after configuring the attack detection circuitry, starting, by the boot sequencing system, a root of trust processor to initiate a boot sequence;
- configuring, by the boot sequencing system, a second internal clock signal from a second clock source based on trim information accessed from the first storage device;
- clocking, by the boot sequencing system, the root of trust processor using the second internal clock signal;
- and
- enabling access, by the root of trust processor during the boot sequence, to information stored in a second storage device.
A method comprising:
- configuring, by a boot sequencing system, attack detection circuitry based on configuration information accessed from a first storage device;
- after configuring the attack detection circuitry, starting, by the boot sequencing system, a root of trust processor to initiate a boot sequence;
- enabling access, by the root of trust processor during the boot sequence, to information stored in a second storage device;
- and
- prior to configuring the attack detection circuitry based on the configuration information, enabling, by the boot sequencing system, operation of the attack detection circuitry to monitor for voltage glitching attacks.
A system comprising:
- a processor;
- attack detection circuitry;
- a first storage device;
- a second storage device;
- and
- a boot sequencer configured to:
- receive, on a port, a voltage;
- responsive to receiving the voltage on the port, generate an internal reset signal and a first internal clock signal from a first clock source;
- configure the attack detection circuitry based on information accessed from the first storage device;
- after configuring the attack detection circuitry, start the processor;
- configure a second internal clock signal from a second clock source based on trim information accessed from the first storage device;
- and
- clock the processor using the second internal clock signal;
- and
- enable access, by the processor, to secure data stored in the second storage device.
A system comprising:
- a first clock;
- a second clock;
- attack detection circuitry;
- a storage device;
- and
- a boot sequencer configured to:
- configure, while being clocked by the first clock from a first clock source, the attack detection circuitry based on configuration information stored in the storage device,
- configure, while being clocked by the first clock, the second clock from a second clock source based on trim information stored in the storage device, and
- after configuring the second clock, select the second clock for use in further boot sequencing operations.
Dependencies are inferred from the claim text.