Back to results
US 11,636,176 B2Granted
Interpolation method and apparatus for arithmetic functions
AssigneeApple Inc.
InventorsWilliam C. Athas, Zaid M. Nadeem, Tetiana Parshakova
Life of this patent
Estimating the term…
Abstract
An interpolation circuit included in a computer system may receive an operand that includes a plurality of bits occupying respective ones of a plurality of ordered bit positions, and generate multiple conditionally-negated values of respective portions of the operand starting at corresponding bit positions. The interpolation circuit may combine the operand and the plurality of conditionally-negated values to generate an approximation of a result of an arithmetic operation performed on the operand.
Claims15
An apparatus, comprising:
- a plurality of exclusive-OR logic gates configured to:
- receive an operand that includes a plurality of bits occupying respective ones of a plurality of ordered bit positions;
- and
- perform a plurality of exclusive-OR operations using a bit value at a particular one of a plurality of ordered bit positions and respective ones of a remaining set of bits of the plurality of bits to generate a plurality of result bits, wherein the remaining set of bits occupy bit positions of the plurality of ordered bit positions that are less significant than the particular one of the ordered bit positions;
- an adder circuit that includes a plurality of single-bit adder circuits including a given single-bit adder circuit configured to add an input bit and a carry-in bit to generate an output bit and a carry-out bit, wherein the adder circuit is configured to:
- add the bit value of the particular one of the plurality of ordered bit positions and a sum of the plurality of result bits to generate a conditionally-negated value of a corresponding portion of the operand;
- and
- generate a corresponding term of one or more of terms using the conditionally-negated value and a value of a bit occupying the particular one of the ordered bit positions;
- and
- an output circuit that includes a plurality of flip-flop circuits arranged in a chain, in which an output of a particular flip-flop circuit is coupled to an input of a next flip-flop in the chain, wherein the output circuit is configured to combine the operand and the one or more of terms to generate an approximation of a result of an arithmetic operation performed on the operand.
7 more elements
A method, comprising:
- receiving, by a plurality of exclusive-OR gates, data indicative of an arithmetic operation and an operand that includes a plurality of bits occupying respective ones of a plurality of ordered bit positions;
- performing, by the plurality of exclusive-OR gates, a plurality of exclusive-OR operations using a bit value at a particular bit position of the plurality of ordered bit positions and respective ones of a remaining set of bits of the plurality of bits to generate a plurality of result bits, wherein the remaining set of bits occupy bit positions of the plurality of ordered bit positions that are less significant than the particular bit position;
- adding, by an adder circuit that includes a plurality of single-bit adder circuits, the bit value at the particular one of the plurality of ordered bit positions and a sum of the plurality of result bits to generate a particular conditionally-negative value of a plurality of conditionally-negated values of respective portions of the operand;
- wherein adding the bit value at the particular one of the plurality of ordered bit positions and the sum of the plurality of result bits includes adding, by a given single-bit adder circuit of the plurality of single-bit adder circuits, adding the bit value and a carry-in bit from a proceeding stage of the plurality of single-bit adder circuits to generate an output bit and a carry-out bit;
- and
- combining, by an output circuit that includes a plurality of flip-flop circuits arranged in a chain, in which an output of a particular flip-flop circuit is coupled to an input of a next flip-flop in the chain, the operand and the plurality of conditionally-negated values to generate an approximation of a result of the arithmetic operation performed on the operand.
3 more elements
Dependencies are inferred from the claim text.